• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.4
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• pp.9-16
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• 2000

This paper shows the performance of a multiuser detection DS-CDMA receiver based on of the hybrid scheme of parallel interference cancellation (PIC) and successive interference cancellation (SIC). The proposed hybrid interference cancellation is presented and is compared with existing PIC, SIC and Hybrid It of other type schemes. The performance criteria used for comparison are complexity, delay and average bit error rate (BER) performance obtained by simulation in Rayleigh-fading channel (Jake's model) with additive white Gaussian noise (AWGN). In the proposed hybrid IC, the BER performance approximates the one of SIC and the delay is half of the SIC. And the number of cancellation of the hybrid It is reduced about a fourth.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of IKEEE
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• v.24 no.1
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• pp.368-371
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• 2020

In this paper, we propose a linear tapered slot rectifying antenna for a portable UHF-band RFID system. Since the proposed rectifying antenna does not use a dielectric substrate, the planar antenna is implemented with a thin metal thickness. The rectifier circuit converts input RF power into output DC voltage using a voltage doubler circuit based on two anti-parallel schottky diodes. The rectifying antenna is integrated by the voltage doubler circuit into a linear tapered slot antenna. For conjugate impedance matching of the rectifying circuit and the linear tapered slot antenna, the source-pull method was utilized by adjusting the angle of the tapered slot and the length of the antenna feed line. The proposed antenna prototype has been verified with the electrical and radiation characteristics through RF-DC conversion and far-field radiation test in open space measurement environment. Finally, the proposed antenna is realized to 0.23-wavelength (75 mm) and 0.18-wavelength (60 mm) at 915 MHz center frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1188-1193
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• 2004

So far, there have been grossly 3 types of studies on GF(2m) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. Serial multiplication method was first suggested by Mastrovito (1), to be known as the basic CF(2m) multiplication architecture, and this method was adopted in the array multiplier (2), consuming m times as much resource in parallel to extract m times of speed. In 1999, Paar studied further to get the benefit of both architecture, presenting the hybrid multiplication architecture (3). However, the hybrid architecture has defect that only complex ordo. of finite field should be used. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software. The implemented GF(2m) multiplier shows t times as fast as the traditional one, if we modularized the numerical expression by t number of parts.

• The KIPS Transactions:PartA
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• v.10A no.2
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• pp.123-130
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• 2003

This paper presents a new striped checkpointing scheme for serverless cluster computers, where the local disks are attached to the cluster nodes collectively form a distributed RAID with a single I/O space. Striping enables parallel I/O on the distributed disks and staggering avoids network bottleneck in the distributed RAID. We demonstrate how to reduce the checkpointing overhead and increase the availability by striping and staggering dynamically for communication intensive applications. Linpack HPC Benchamark and MPI programs are applied to these checkpointing schemes for performance evaluation on the 16-nodes cluster system. Benchmark results prove the benefits of the striped checkpointing scheme compare to the existing schemes, and these results are useful to design the efficient checkpointing scheme for fast rollback recovery from any single node failure in a cluster system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1371-1382
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• 2000

IMT-2000 system is the third generation mobile communication system which aims at mobile multimedia services with global roaming. Like 2nd generation system, the IMT-2000 system is also under strong influence of interferences among active subscribers in the multiple access environment. That is, in multiple access environment, signals from one subscriber could interfere with others in the same cell or in the neighboring cells. The interference control in the IMT-2000 systems is much more difficult then the interference control in the 2ndgeneration CDMA cellular systems, since the transmitted power of a subcriber might be different that of others in the IMT-2000 system. In this paper, a parallel interference cancellation with traffic discrimination is proposed which can effectively cancel interferences by grouping the subscribers into several equi-power classes. As a conclusion, simulation results show that the proposed method outperforms the conventional partial PIC scheme in several aspects.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.10
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• pp.413-420
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• 2013

Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

• Journal of Digital Convergence
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• v.17 no.12
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• pp.197-202
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• 2019

In line with the era of the 4th Industrial Revolution, 5G technology has become common technology, and 5G technology is evaluated as a technology that minimizes the speed and response speed compared to 4G using technologies such as network slicing and ultra-multiple access. 5G NR stands for 5G mobile communication standard, and network slicing cuts the network into parallel connections to optimize the network. In addition, the risk of hacking is increasing as data is processed in the base station unit. In addition, since the number of accessible devices per unit area increases exponentially, there is a possibility of base station attack after hacking a large number of devices in the unit area. To solve this problem, this study proposes the introduction of quantum cryptography and 5G security standardization.

• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1147-1156
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• 2001

In this paper, a new design architecture of radar signal processor in real time is proposed. It has been designed and implemented under the consideration to minimize the inter-processor communication overhead and to maintain the coherence in Doppler pulse domain and in range domain. Its structure can be easily reconfigured and reprogrammed in accordance with an addition of function algorithm or a modification of operational scenario. As we designed a task configuration for parallel processing from measures of computation time for function algorithms and transmission time for results by signal processing, data exchange between processors for performing of function algorithms could be fully removed. Morocco-2 board equipped ADSP-21060 processor of Analog Devices inc. and APEX-3.2 developed for SHARC DSP were used to construct the radar signal processor.