• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.444-447
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• 2011

In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.239-239
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• 2004

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2004.07a
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• pp.327-327
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• 2004

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.38-39
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• 1986

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.9
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• pp.893-900
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• 1991

And this system is compared with past knapsack system by implementation of low density attack in Brickell and Lagarias, Odlyzko’s method. Also the VLSI architecture for parallel implementation of this linearly shift knapsack system is presented

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.25-27
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• 1984

Using LED sources, the system that performs optical logic function of the input data arrays will be presented. Sixteen possible functions of two binary data arrays, such as AND, OR, NOR and XOR are simply obtained in parallel by controlling LED switching mode. Experimental result and some examples of application will be given.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.210-210
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• 2004

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.280-280
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• 2004

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.23-33
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• 2000

We propose a model which overlaps communication with computation for efficient communication in the data-parallel programming paradigm. The overlapping model divides a given loop partition into several sub-partitions to obtain computation which can be overlapped with communication. A loop partition sometimes refers to other data partitions, but not all iterations in the loop partition require non-local data. So, a loop partition may be divided into a set of loop iterations which require non-local data, and a set of loop iterations which do not. Each loop sub-partition is dynamically scheduled depending on associated message arrival, The experimental results for a few benchmarks in IBM SP2 show enhanced performance in our overlapping model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.