• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.144-154
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• 2011

In this paper, we propose a parallel LDPCA encoding method for fast transform-domain Wyner-Ziv video encoding which is suitable in an ultra fast and low power video encoding. The conventional transform-domain Wyner-Ziv video encoding performs LDPCA channel coding of quantized transform coefficients in bitplane-serial fashion, which takes about 60% of total encoding time, and this computational complexity becomes severer as the bitrate increases. The proposed method binds several bitplanes into one packed message and carries out the LDPCA encoding in parallel. The proposed LDPCA encoding method improves the encoding speed by 8 ~ 55 times. In the experiment, the proposed Wyner-Ziv encoder can encode 700 ~ 2,300 QCIF size frames per second with GOP=64. The method can be applied to the pixel-domain Wyner-Ziv encoder using LDPCA, and has a wide scope of application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.2
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• pp.163-171
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• 2016

In order to detect the exact position of high-speed train, it is necessary to obtain location information from the transponder tag installed along the track. In this paper, we proposed parallel descrambling scheme for high-speed railway transponder system, which aims for reducing the processing time required to decode telegram. Since a telegram is stored in a tag after information bits are scrambled by an encoder, decoding procedure includes descrambling of received telegram to recover the original information bits. By analyzing the structure of the descrambling shift register circuit, we proposed a parallel descrambling scheme for fast decoding of telegram. By comparing the required number of clocks, it is shown that the proposed scheme significantly outperforms the original one.

• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.378-389
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• 1999

Parallel tasks in distributed real-time systems can be divided into several subtasks and be executed in parallel according to their real-time attributes. But, it is difficult to gain the optimal solution which is to allocate a tasks deadline into the subtasks deadline while minimizing the subtasks deadline miss. Tn this Paper, we propose the algorithm that allocates deadlines into each subtask, according to the attributes of each subtask(i.e. using communication time and execution time to periodic tasks). Also, we suggest a processor mapping algorithm that considers the communication time among the processors and the effective duplication algorithm which is allocated to the identical processor for the purpose of improving the communication time between the subtasks. We can obtain a result that reduces IPC(Inter-Processor Communication) time and uses the idle processor through applying effective real-time attributes to FUTD(Fully connected, Unbounded Task Duplication) algorithms. As a result, we can improve the average processor utilization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.91-97
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• 2000

With the brilliant development of information communication and the rapid spread of internet, current network communication is carrying several up-to-date functions such as electronic commerce, activation of electro currency or electronic signature and will produce more advanced services in the future. Information communication network such as that electronic commerce would demand the more safe and transparent guard of network, and anticipate the more fast performance of network. In this paper, in order to meet the several demands, DES(data encryption standard) with parallel feistel structure, which feistel structure of the basic structure of DES is transformed into in parallel, is proposed. The existing feistel structure can't use pipeline method for the structural problem of DES itself-the propagation of error. therefore, this modified parallel feistel structure could improve largely the performance of DES which had to have the trade-off relation between data processing speed and data security and in addition a method proposed in SEED having adopted the modified parallel feistel structure shows more excellent secure function and/or fast processing ability. The used CAD Tool use Synopsys Ver. 1999. 10 in both of synthesis and simulation.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.309-312
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• 2004

This paper proposes the architecture of UWB OFDM communication system. More high data rate is requested in the 128-point FFT/IFFT of the UWB OFDM communication system than the conventional communication systems. So, the proposed architecture uses pipeline and parallel architecture. For a highly efficient architecture, the optimal clipping power and the input quantization bits are found in simulation. The hardware complexity of the proposed architecture is presented is consideration of Adder, Register and Complex Multiplier.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.480-483
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• 1997

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed to develope real-time simulators. Vital points of real-time simulators are accuracy, computing speed, and deadline observing. In this paper, we present a enhanced strategy in which we can provide powerful computing power by parallel processing of DSP processors with communication links. We designed general purpose DSP modules, and a VME interface module. Because the DSP module is designed for general purpose, we can easily expand the parallel system by just connecting new DSP modules to the system. Additionally we propose methods about downloading programs, initial data to each DSP module via VME bus, DPRAM and processing sequences about computing and updating values between DSP modules and CPU30 board when the simulator is working.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1598-1602
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• 2003

The parallel-type mechanism provides more accurate and stiff motion than the serial-type mechanism. However, in case of using the haptic device, the performance of the force reflection can be deteriorated due to the singular points existing in workspace. In this paper, we propose a redundantly actuated parallel 3-DOF haptic device, which is singularity-free in the workspace and has an improved force reflection capability. In addition, we propose a new force distribution algorithm, which can reflect force of both high and low resolution, using two sets of actuator with different size. Redundant actuators are attached to the base frame in order to minimize the inertia of the system. Moreover, a wire and gear reduction system is employed to achieve high force reflection along with soft feeling. We confirm the performance of the force reflection capability throughout simulation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.13-26
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• 1993

Motion picture algorithms are realized on the multiprocessor system presented in the Study I. For the most efficient processing of the algorithms, pipelining and geometrical parallel processing methods are employed, and processing time, communication load and efficiency of each algorithm are compared. The performance of the implemented system is compared and analysed with reference to MPEG coding algorithm. Theoretical calculations and experimental results both shows that geometrical partitioning is a more suitable parallel processing algorithm for moving picture coding having the advantage of easy algorithm modification and expansion, and the overall efficiency is higher than pipelining.

• Bulletin of the Korean Chemical Society
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• v.24 no.6
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• pp.733-738
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• 2003

Linear scaling quantum theories are reviewed especially focusing on the method adopted in GAMESS. The three key translation equations of the fast multipole method (FMM) are deduced from the general polypolar expansions given earlier by Steinborn and Ruedenberg. Simplifications are introduced for the rotation-based FMM that lead to a very compact FMM formalism. The OPS (optimum parameter searching) procedure, a stable and efficient way of obtaining the optimum set of FMM parameters, is established with complete control over the tolerable error ε. In addition, a new parallel FMM algorithm, requiring virtually no inter-node communication, is suggested which is suitable for the parallel construction of Fock matrices in electronic structure calculations.

• Journal of information and communication convergence engineering
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• v.14 no.3
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• pp.184-190
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• 2016

We present experimental demonstrations of electromagnetic bandgap (EBG) structures for the wideband suppression of radiated emissions from a power bus in high-speed printed circuit boards (PCBs). In most of the PCB designs, a parallel plate waveguide (PPW) structure is employed for a power bus. This structure significantly produces the wideband-radiated emissions resulting from parallel plate modes. To suppress the parallel plate modes in the wideband frequency range, the power buses based on the electromagnetic bandgap structure with a defected ground structure (DGS) are presented. DGSs are applied to a metal plane that is connected to a rectangular EBG patch by using a via structure. The use of the DGS increases the characteristic impedance value of a unit cell, thereby substantially improving the suppression bandwidth of the radiated emissions. It is experimentally demonstrated that the DGS-EBG structure significantly mitigates the radiated emissions over the frequency range of 0.5 GHz to 2 GHz as compared to the PPW.