• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.8
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• pp.15-23
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• 1992

Neural network control has many innovative potentials for fast, accurate and intelligent adaptive control. In this paper, two kinds of neurocontrol architectures for the dynamic control of robot manipulators are developed. One is based on a System Identification and Control scheme and the other is based on the Feedback-Error leaming scheme. Both of the proposed architectures use an inverse dynamic neurocontroller in parallel with a linear neurocontroller. The difference is that the first architecture uses the system identifier to get the signals used for training neurocontrollers, while the second architecture uses a properly defined energy function. Compared with the previous types of neurocontrollers which are using an inverse dynamic neurocontroller and a fixed PD gain controller, the proposed architectures not only eliminate the painful process of the fixed gain tuning but also exhibit superior peformances because the linear neurocontroller can adapt its gains according to the applied task. This superior performance is tested and verified through computer simulation of the dynamic control of the PUMA 560 arm.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.161-170
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• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.76-84
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• 1994

This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.537-540
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• 2000

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.27-34
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• 1994

Block matching motion estimation is the most widely used method for motion compensated coding of image sequences. Based on a two dimensional systolic array, VLSI architecture and implementation of the full search block matching algorithm are described in this paper. The proposed architecture improves conventional array architecture by designing efficient processing elements that can control the data prodeuced by efficient search window division method. The advantages are that 1) it allows serial input to reduce pin counts for efficient composition of local memories but performs parallel processing. 2) It is flexible and can adjust to dimensional changes of search windows with simple control logic. 3) It has no idel time during the operation. 4) It can operate in real/time for low and main level in MPEG-2 standard. 5) It has modular and regular structure and thus is sutiable for VLSI implementation.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.306-312
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• 2000

In this paper, the efficient architecture of small Reed-solomon architecture is suggested. Here, 3-stage pipeline is adopted. In decoding, error-location polynomials are obtained by BMA using fast iteration method, and syndrome polynomials, where calculation complexity is required, are obtained by parallel calculation using ROM table, and the roots of error location polynomial are calculated by ROM table using Chein search algorithm. In the suggested decoder, it is confirmed that 3 symbol random errors can be corrected and 124Mbps decoding rate is obtained using 25 Mhz system clock.

• MALSORI
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• no.60
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• pp.125-144
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• 2006

W3C announced a standard software architecture for multimodal context-aware middleware that emphasizes modularity and separates structure, contents, and presentation. We implemented a distributed multimodal interface system followed the W3C architecture, based on SCXML. SCXML uses parallel states to invoke both XHTML and VoiceXML contents as well as to gather composite or sequential multimodal inputs through man-machine interactions. We also hire Delivery Context Interface(DCI) module and an external service bundle enabling middleware to support context-awareness services for real world environments. The provision of personalized user interfaces for mobile devices is expected to be used for different devices with a wide variety of capabilities and interaction modalities. We demonstrated the implemented middleware could maintain multimodal scenarios in a clear, concise and consistent manner by some experiments.