• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.149-153
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• 2019

The technology of electronic packaging among semiconductor technologies is evolving as an axis of the market in its own field beyond the simple assembly process of the past. In the field of electronic packaging technology, the packaging of power modules plays an important role for green electric vehicles. In this power module packaging, the thermal reliability is an important factor, and silicon nitride plays an important part of package substrates, Silicon nitride is a compound that is not found in nature and is made by chemical reaction between silicon and nitrogen. In this study, this core material, silicon nitride, was fabricated by reaction bonded silicon nitride. The fabricated silicon nitride was studied for thermo-mechanical properties, and through this, the structure of power module packaging was made using reaction bonded silicon nitride. And the characteristics of stress were evaluated using finite element analysis conditions. Through this, it was confirmed that reaction bonded silicon nitride could replace the silicon nitride as a package substrate.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.1-6
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• 2013

3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D IC technology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging. However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturing yield, and device test. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling system has been reviewed as one of device cooling methods for the next generation thermal management.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.5
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• pp.350-354
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• 2020

In this study, a pressure sensor for each displacement was fabricated based on the silicon-based pressure sensor obtained through simulation results. Wires were bonded to the pressure sensor, and a piezoresistive pressure sensor was inserted into the printed circuit board (PCB) base by directly connecting a micro-electro-mechanical system (MEMS) sensor and a readout integrated circuit (ROIC) for signal processing. In addition, to prevent exposure, a non-conductive liquid silicone was injected into the sensor and the entire ROIC using a pipette. The packaging proceeded to block from the outside. Performing such packaging, comparing simple contact with strong contact, and confirming that the measured pulse wavelength appears accurately.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.165-165
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• 2009

현재 반도체나 이동통신 분야는 사용자의 요구에 따라 PCB의 회로선폭이 갈수록 좁아지고 있다. 이러한 정밀 부품을 제조하기 위한 제조공정에서 각광받기 시작한 기술 중 하나가 대기압 플라즈마 기술이다. 본 연구에서는 미세패턴 형성이 가능한 에폭시 본딩 필름위에 무전해 도금공정을 통한 패턴 도금법을 이용하여 패턴을 형성하였고, 형성된 패턴에 대기압 플라즈마 처리 횟수에 따른 접촉각(Contact Angle)과 Peel Strength의 변화를 분석하였다. 또한 에폭시 본딩 필름을 이용한 Build-up공정을 거쳐 Micro Via를 형성하여 대기압 플라즈마 처리 횟수에 따른 Via 표면을 분석하였다. 대기압 플라즈마 기술은 진공식에 비해 소규모 장비를 이용한 전처리가 가능하고, 초기 설비비용을 절감하는데 탁월한 효과가 있어 널리 사용하는 기술 중 하나이다. 이 연구를 통하여 대기압 플라즈마 처리 횟수에 따른 표면에너지의 변화로 인한 접촉각이 좋아지는 것을 알 수 있으며, 대기압 플라즈마 처리를 한 패턴표면이 친수성으로 변하면서 현상된 드라이 필름 사이로 도금액이 원활히 공급되어서 미세패턴 모양이 우수하게 구현되었음을 알 수 있었다. 또한 Via Filling에도 뛰어난 효과가 있었음을 확인할 수 있었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.145-156
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• 2005

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.43-48
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• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• The monthly packaging world
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• s.241
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• pp.88-91
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• 2013

인쇄산업에 있어서 브랜드 컬러 매니지먼트를 비롯한 인쇄 표준화의 중요성이 점차 부각되고 있는 현재, CMS(Color Management System)를 통해서 정량적으로 인쇄품질을 관리함으로써 그라비어 인쇄업계 발전을 선도하고 있는 업체가 있어 이목을 끌고 있다.

• The monthly packaging world
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• s.77
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• pp.154-155
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• 1999

새로운 저항가열 보트컨트롤 방식은 증착공정의 가격을 절하시키면서 증착 품질은 월등히 향상시킬 것이다. 심지어는 지금까지의 기존 저항 가열방식으로는 성공할 수 없었던 금$\cdot$은 사용으로도 적용할 수 있는 새로운 세상을 열게 될 것이다.