• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.210-210
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• 2007

RF circuit을 구현하는데 있어서 기판의 전기적 특성을 정확하게 아는 것은 매우 중요하다. 왜냐하면 초고주파로 갈수록 기판의 전기적인 특성이 circuit에 많은 영향을 미치고 이러한 영향을 고려한 circuit를 설계해야 원하는 결과를 얻을 수 있기 때문이다. 본 연구에서는 현재 사용되고 있는 PI 기판의 전기적인 특성인 유효 유전율과 loss tangent 값을 캐패시터를 이용해 정확하게 측정하고자 했다. 캐패시터의 conductor material은 Cu를 사용하였고 PI 기판의 투께는 25um 를 이용하였다. PI 기판의 유효 유전율은 캐패시터 측정에 의한 data률 EM simulation tool 을 통해 분석한 후 간단한 수식에 의해 구했다. 또한 PI 기판의 loss tangent 값을 구하기 위해 캐패시터의 dissipation factor를 분석하였다. 캐패시터의 dissipation factor는 dielectric loss, AC 저항에 의한 loss, DC 저항에 의한 loss를 포함한다, DC 저항에 의한 loss는 dissipation factor에 차지하는 비율이 낮기 때문에 생략이 가능하다. 하지만 AC 저항에 의한 loss는 주파수에 비례하여 값이 커지게 된다. 따라서 주파수가 올라 갈수록 dissipation factor도 상승하게 되는데 주파수의 전 대역에서 AC 저항에 의한 loss를 보정해주면 dielectric loss를 얻을 수 있다. 추출된 dielectric loss를 통해 PI 기판의 loss tangent 값을 구하였다. 캐패시터를 이용한 PI 기판의 전기적 특성 추출은 간단한 구조를 통해 얻을 수 있기 때문에 다른 재료의 기판의 전기적 특성을 추출하는데도 이용이 용이하다.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• 마이크로전자및패키징학회지
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• 제30권4호
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• pp.50-60
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• 2023

BGA(ball grid array)는 높은 집적도와 우수한 방열 성능을 갖고 있어 널리 이용되는 방식의 패키지이다. BGA에서 솔더볼은 패키지와 PCB를 전기적으로 연결하는 중요한 역할을 하므로, 다양한 기계적 하중 하에서 솔더볼의 비탄성 변형을 이해하는 것은 반도체 패키지의 강건설계에 필수적이다. 본 연구에서는 공정 중 PCB의 휨, die와 substrate 간의 열팽창 계수 차이 등으로 인해 소성변형이 발생한 솔더볼의 초기 형상이 비탄성 변형과 파단에 미치는 영향을 유한요소 해석으로 분석하였다. 시뮬레이션 결과, shear와 bending 하중에서 tilted, hourglass 형상 모두 파단이 발생한 반면, compression 하중이 작용하는 경우는 모두 파단이 발생하지 않았다. Shear와 bending 하중에 compression이 각각 결합될 경우, 응력삼축비가 0보다 작은 값으로 유지되어 파단이 억제되었다. 또한 변형에 취약한 요소의 Lagrangian-Green 변형률 텐서를 이용해 비교한 결과, 동일한 하중 조건이라도 솔더볼의 형상에 따라 변형의 양상에 유의미한 차이가 있음을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 춘계학술대회 및 기술 세미나 논문집 디스플레이 광소자
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• pp.42-42
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• 2008

Considerable attention has been focused on the applications of flexible liquid crystal (LC)-based displays because of their many potential advantages, such as portability, durability, light weight, thin packaging, flexibility, and low power consumption. To develop flexible LCDs that are capable of delivering high-quality moving images, like conventional glass-substrate LCDs, the LC device structure must have a stable alignment layer of LC molecules, concurrently support uniform cell gaps, and tightly bind two flexible substrates under external tension. However, stable LC molecular alignment has not been achieved because of the layerless LC alignment, and consequently high-quality images cannot be guaranteed. To solve these critical problems, we have proposed a PDMS pixel-wall based bonding method via the IB irradiation was developed for fasten the two substrates together strongly and maintain uniform cell gaps. The effect of the IB irradiation on PDMS with PI surface was also evaluated by side structure configuration and a result of x-ray photoelectron spectroscopic analysis of PDMS interlayer as a function of binder with substrates. large number of PDMS pixel-walls are tightly fastened to the surface of each flexible substrate and could maintain a constant cell gap between the LC molecules without using any other epoxy or polymer. To enhance the electro-optical performance of the LC device, we applied an alignment method that creates pretilt angle on the PI surface via ion beam irradiation. Using this approach, our flexible LCDs have a contrast ratio of 132:1 and a response time of about 15 ms, resulting in highly reliable electro-optical performance in the bent state, comparable to that of glass-substrate LCDs.

• 한국재료학회지
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• 제20권9호
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• pp.494-499
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• 2010

Tin oxide thin films were prepared on borosilicate glass by rf reactive sputtering at different deposition powers, process pressures and substrate temperatures. The ratio of oxygen/argon gas flow was fixed as 10 sccm / 60 sccm in this study. The structural, electrical and optical properties were examined by the design of experiment to evaluate the optimized processing conditions. The Taguchi method was used in this study. The films were characterized by X-ray diffraction, UV-Vis spectrometer, Hall effect measurements and atomic force microscope. Tin oxide thin films exhibited three types of crystal structures, namely, amorphous, SnO and $SnO_2$. In the case of amorphous thin films the optical band gap was widely spread from 2.30 to 3.36 eV and showed n-type conductivity. While the SnO thin films had an optical band gap of 2.24-2.49 eV and revealed p-type conductivity, the $SnO_2$ thin films showed an optical band gap of 3.33-3.63 eV and n-type conductivity. Among the three process parameters, the plasma power had the most impact on changing the structural, electrical and optical properties of the tin oxide thin films. It was also found that the grain size of the tin oxide thin films was dependent on the substrate temperature. However, the substrate temperature has very little effect on electrical and optical properties.

• 마이크로전자및패키징학회지
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• 제31권3호
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• pp.72-79
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• 2024

2.xD 패키지 구조에서 고속, 고대역폭 실현을 위해 인터포저 (Interposer) 혹은 브리지 다이와 이종 칩 간 접합 공정에 높은 기술력을 요하는 공법이 연구되고 있다. 특히 접합면 연삭 (Grinding) 공정은 그 핵심 기술에 속한다. Cu layer를 포함한 인터포저나 브리지 다이를 기판에 접합한 후 Cu처럼 전기적 연결이 가능한 금속 소재를 연삭 공정으로 노출하여 이종 칩을 서로 연결하는 방식은 종래의 패키징 기술을 그대로 활용하는 공법이다. 다만, 2.xD 패키지처럼 미세 범프의 대량 접합 공정에서 양산 가능한 수율과 품질을 충족하려면 높은 정밀도를 기반으로 한 공법 개발이 요구된다. 본 논문에서는 2.xD 패키지 구조의 이종 칩 접합을 위한 다중 가공물 연삭 과정에서 연삭 휠의 입도를 변수로 하여 패키지 연삭을 진행하였고, 노출된 가공물의 표면 양상 및 접합 특성에 관해 연구하였다. 본 연구의 고찰을 통해 고품질 접합을 위한 연삭 공정을 최적화하여 첨단 패키징 기술 발전에 기여할 수 있을 것이라 기대한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.269-272
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• 2004

Printed circuit boards (PCB) replaced conventional wiring in most electronic equipment I, reducing the size and weight of electronic equipment while improving reliability, uniformity, precision and performance. PCB is used in all kinds of electronic products because they can be mass-produced with very high circuit density and also enable easier trouble-shooting. This paper presents the analyses of the patent information of Build-up PCB which is seen as the most promising solution, as its substrate supports multi-level packaging, thinner board profiles and smaller pitches.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.63-67
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• 2008

The charged particle type display is a kind of electronic paper showing information images using positive and negative charged particles ($<10{\mu}m$). In this work we used yellow(-) and black(+) particles which are respectively addressed to the cells of a upper and a rear substrate by using electric field. Our independent addressing method has strong points compared to the mixed particle putting method. The packaging with two orthogonal substrates and the aging process is followed by addressing process. The panel is sequentially driven by matrix method for each 4-unit cells. Layers of particles are controlled by barrier ribs and must be addressed to minimum 2 layers.

• The Korean Journal of Ceramics
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• 제1권2호
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• pp.96-100
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• 1995

Recently, alumina/glass composites have been applied as a substrate material for hybrid IC and LSI multi-chip packaging. In this study, the characterization of sodium borosilicate glasses containing NaF and $AlF_3$ and the preparation of the resulted glass/alumina composites have been examined and the effect of the addition of fluorides on the thermal. and dielectric properties of the sintered composites have been studied. The sintering temperature of specimens was lowered by about 100-$150^{\circ}C$ by the addition of fluorine compared with the specimens without fluorine. The specimens containing fluorine showed slightly lower dielectric constants than those of the specimens without fluorine.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.1005-1008
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• 2003

We report a new FCOG (flip chip on glass) technique using solder bumps for display packaging applications. The In and Sn solder bumps of 40 ${\mu}m$ pitches were formed on Si and glass substrate. The In and Sn bumps were bonded at 125 at the pressure of 3 mN/bump. The metallurgical bonding was confirmed using cross-sectional SEM. The contact resistance of the solder joint was 65 $m{\Omega}$ which was much lower than that of the joint made using the conventional ACF bonding technique. We demonstrate that the new COG technique using solder bump to bump direct bonding can be applied to advanced LCDs that lead to require higher quality, better resolution, and lower power consumption.