• Title/Summary/Keyword: package method

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The Study of Quality Control for Package Printing (포장 인쇄의 인쇄적성 향상에 관한 연구)

  • Lee, Man-Gyo;Ha, Young-Baeck;Youn, Jong-Tae
    • Journal of the Korean Graphic Arts Communication Society
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    • v.23 no.1
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    • pp.53-63
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    • 2005
  • The quality of the print can be specified through the quality of the coloring, the reproduction of fine structures and the range of tone values. Also, package printed quality are controlled by this points. In this paper, densitometry method was used for printed quality. By densitometry we can get the print density and the parameters of each conditions that characterize halftone printing, such as dot gain and relative printing contrast. Also, we have proposed the optimizes range of the parameters such as density, dot gain etc. to the package printed printability control.

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A Design Methodology for The Minimum DIE Area of Power MOSFET's Considering Thermal Resistance of the Package (Package 의 열저항을 고려한 전력용 MOSFET의 최소 DIE 면적 설계)

  • Kim, Soo-Seong;Kim, Il-Jung;Choi, Yearn-Ik;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.1286-1288
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    • 1993
  • An analytical method for the optimum design of the minimum die size in power MOSFETs is presented. The proposed methodology considers the thermal resistance of the package and gives the minimum die area for desired drain current levels. The results are compared with experimental data and it is found that the die size mar be reduced if it is designed according to the proposed design procedure.

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An Example of Development and Application of PBL Package (문제중심학습 패키지 개발 및 적용의 일 예)

  • Je, Mi-Soon;Choi, Won-Hee
    • Journal of Korean Academy of Fundamentals of Nursing
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    • v.14 no.3
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    • pp.351-360
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    • 2007
  • Purpose: The purpose of this study was to develop a Problem-Based Learning (PBL) package, test its application and evaluate students' recognition of the effectiveness of PBL in nursing colleges. Method: Thirteen steps were used in the process developing the PBL package. After its application, the first questionnaire for self-evaluation and satisfaction with PBL class was given to 94 nursing students in December, 2005. To further evaluate the students' recognition of the effectiveness of PBL, a second questionnaire was given to 83 nursing students out of the 96 in May, 2007 after clinical practice. Data analysis was conducted using means with standard deviation. Results: The results of students' self-evaluation showed high achievement in learning outcome and process using the PBL method. Also, they expressed satisfaction with the subject management, the lecturer and their peers after the PBL class. Students recognized that the PBL class had positive effectiveness in clinical practice and wanted more PBL classes and the inclusion of complex cases from well designed packages. Conclusion: PBL class could be considered as an opportunity to fortify student nurses' abilities to adjust to the real clinical situation.

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Automatic Classification of SMD Packages using Neural Network (신경회로망을 이용한 SMD 패키지의 자동 분류)

  • Youn, SeungGeun;Lee, Youn Ae;Park, Tae Hyung
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.3
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    • pp.276-282
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    • 2015
  • This paper proposes a SMD (surface mounting device) classification method for the PCB assembly inspection machines. The package types of SMD components should be classified to create the job program of the inspection machine. In order to reduce the creation time of job program, we developed the automatic classification algorithm for the SMD packages. We identified the chip-type packages by color and edge distribution of the images. The input images are transformed into the HSI color model, and the binarized histroms are extracted for H and S spaces. Also the edges are extracted from the binarized image, and quantized histograms are obtained for horizontal and vertical direction. The neural network is then applied to classify the package types from the histogram inputs. The experimental results are presented to verify the usefulness of the proposed method.

A Prediction of Chip Quality using OPTICS (Ordering Points to Identify the Clustering Structure)-based Feature Extraction at the Cell Level (셀 레벨에서의 OPTICS 기반 특질 추출을 이용한 칩 품질 예측)

  • Kim, Ki Hyun;Baek, Jun Geol
    • Journal of Korean Institute of Industrial Engineers
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    • v.40 no.3
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    • pp.257-266
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    • 2014
  • The semiconductor manufacturing industry is managed by a number of parameters from the FAB which is the initial step of production to package test which is the final step of production. Various methods for prediction for the quality and yield are required to reduce the production costs caused by a complicated manufacturing process. In order to increase the accuracy of quality prediction, we have to extract the significant features from the large amount of data. In this study, we propose the method for extracting feature from the cell level data of probe test process using OPTICS which is one of the density-based clustering to improve the prediction accuracy of the quality of the assembled chips that will be placed in a package test. Two features extracted by using OPTICS are used as input variables of quality prediction model because of having position information of the cell defect. The package test progress for chips classified to the correct quality grade by performing the improved prediction method is expected to bring the effect of reducing production costs.

Giga-Hertz-Level Electromagnetic Field Analysis for Equivalent Inductance Modeling of High-Performance SoC and SiP Designs

  • Yao Jason J.;Chang Keh-Jeng;Chuang Wei-Che;Wang, Jimmy S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.255-261
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    • 2005
  • With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

Single-Phase Current Source Induction Heater with Improved Efficiency and Package Size

  • Namadmalan, Alireza;Moghani, Javad Shokrollahi
    • Journal of Power Electronics
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    • v.13 no.2
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    • pp.322-328
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    • 2013
  • This paper presents a modified Current Source Parallel Resonant Push-pull Inverter (CSPRPI) for single phase induction heating applications. One of the most important problems associated with current source parallel resonant inverters is achieving ZVS in transient intervals. This paper shows that a CSPRPI with the integral cycle control method has dynamic ZVS. According to this method, it is the Phase Locked Loop (PLL) circuit that tracks the switching frequency. The advantages of this technique are a higher efficiency, a smaller package size and a low EMI in comparison with similar topologies. Additionally, the proposed modification results in a low THD of the ac-line current. It has been measured as less than %2. To show the validity of the proposed method, a laboratory prototype is implemented with an operating frequency of 80 kHz and an output power of 400 W. The experimental results confirm the validity of the proposed single phase induction heating system.

Development of Inspection System for the IC package (반도체 패키지 외관 검사 시스템 개발)

  • Lee, Jung-Seob;Kwon, Oh-Min;Joo, Hyo-Nam;Kim, Joon-Sik;Rew, Keun-Ho
    • Journal of Institute of Control, Robotics and Systems
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    • v.14 no.5
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    • pp.453-461
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    • 2008
  • In this paper, new inspection method is proposed for the surfaces of lead frame and IC's. Optimal optical system and the accurate algorithm for the surface inspection are needed in machine vision area. The proposed optical system is composed of rectangular oblique light illumination and coaxial light illumination for the higher contrast and the results shows the better performances through experiments. The markings of IC surface are inspected using the accurate proposed method using the partitioned correlation coefficient, and the result shows reduction of under kill ratio compared to the previous method.

Automatic Extraction of Component Inspection Regions from Printed Circuit Board by Image Clustering (영상 클러스터링에 의한 인쇄회로기판의 부품검사영역 자동추출)

  • Kim, Jun-Oh;Park, Tae-Hyoung
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.3
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    • pp.472-478
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    • 2012
  • The inspection machine in PCB (printed circuit board) assembly line checks assembly errors by inspecting the images inside of the component inspection region. The component inspection region consists of region of component package and region of soldering. It is necessary to extract the regions automatically for auto-teaching system of the inspection machine. We propose an image segmentation method to extract the component inspection regions automatically from images of PCB. The acquired image is transformed to HSI color model, and then segmented by several regions by clustering method. We develop a modified K-means algorithm to increase the accuracy of extraction. The heuristics generating the initial clusters and merging the final clusters are newly proposed. The vertical and horizontal projection is also developed to distinguish the region of component package and region of soldering. The experimental results are presented to verify the usefulness of the proposed method.

Semiconductor Backend Scheduling Using the Backward Pegging (Backward Pegging을 이용한 반도체 후공정 스케줄링)

  • Ahn, Euikoog;Seo, Jeongchul;Park, Sang Chul
    • Korean Journal of Computational Design and Engineering
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    • v.19 no.4
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    • pp.402-409
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    • 2014
  • Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer information. As a result, it gives the release plan to meet the out target considering current WIP. However, the semiconductor backend process includes the multichip package and test operation for the product bin portion. Therefore, backward pegging method for frontend can't give the release plan for backend process in semiconductor. In this paper, we suggest backward pegging method considering the characteristics of multichip package and test operation in backend process. And we describe the backward pegging problem using the examples.