• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.226-226
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• 2012

The electronic and electrical properties of nickel oxide (NiO) thin films were investigated by reflection electron energy loss spectroscopy (REELS), x-ray photoelectron spectroscopy (XPS), and Hall Effect measurements. REELS spectra revealed that the band gap of the NiO thin film was increased from 3.50 eV to 4.02 eV after annealing the sample at $800^{\circ}C$. Our XPS spectra showed that the amount of Ni2O3 decreased after annealing. The Hall Effect results showed that the doping type of the sample changed from n type to p type after annealing. The resistivity decreased drastically from $4.6{\times}10^3$ to $3.5{\times}10^{-2}$ ${\Omega}{\cdot}cm$. The mobility of NiO thin films was changed form $3.29{\times}10^3$ to $3.09{\times}10^5cm^2/V{\cdot}s$. Our results showed that the annealing temperature plays a crucial role in increasing the carrier concentration and the mobility which leads to lowering resistivity of NiO thin films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Journal of Powder Materials
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• v.14 no.4
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• pp.272-276
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• 2007

P-type thermoelectric material $Si_{0.8}Ge_{0.2}$ was sintered by Hot Press process (HP) and the effect of boron ($0.25{\sim}2$ at%) addition on the thermoelectric properties were reported. To enhance the thermoelectric performances, the $Si_{0.8}Ge_{0.2}$, alloys were fabricated by mechanical alloying (MA) and HP. The carrier of p-type SiGe alloy was controlled by B-doping. The effect of sintering condition and thermoelectric properties were investigated. B-doped SiGe alloys exhibited positive seebeck coefficient. The electrical conductivity and thermal conductivity were increased at the small amount of boron content ($0.25{\sim}0.5$ at%). However, they were decreased over 0.5 at% boron content. As a result, the small addition of boron improved the Z value. The Z value of 0.5 at% B doped $Si_{0.8}Ge_{0.2}$ B alloy was $0.9{\times}10{-4}/K$, the highest value among the prepared alloys.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.195-196
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• 2009

This paper describes the fabrication and characteristics of polycrystalline 3C-SiC thin film diodes for extreme environment applications, in which the this thin film was deposited onto oxidized Si wafers by APCVD using HMDS In this work, the optimized growth temperature and HMDS flow rate were $1,100^{\circ}C$ and 8sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/$SiO_2$/Si(n-type) structure was fabricated and its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) values were measured as 0.84V, over 140V, 61nm, and $2.7{\times}10^{19}cm^2$, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and $500^{\circ}C$ for 30min under a vacuum of $5.0{\times}10^{-6}$Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.131-131
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• 2008

Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used a Monte-Carlo method. We studied the effect of channeling by Al implantation simulation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the Al distribution in 4H-SiC through the variation of the implantation energies and the corresponding ratio of the doses. The implantation energies controlled 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2\times10^{14}$ to $1\times10^{15}cm^{-2}$. In the simulation results, the Al ion distribution was deeper as increasing implantation energy and the doping level increased as increasing implantation doses. After the post-implantation annealing, the electrical properties of Al-implanted p-n junction diode were investigated by SILV ACO ATLAS numerical simulator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.237-238
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• 2008

Electrical properties of Pd/Zn/Pd/Au contacts to p-InP were investigated as function of the V/III ratio of p-InP. P-type InP was made by the Zn diffusion into InP and activation process with rapid thermal annealing (RTA) measurement. After activation, the hole concentration was two orders of magnitude higher than that of the sample having only diffusion process. According to transmission line method (TLM) results, the specific contact resistance of p-InP was lower as used InP having the lower V/III ratio. The experimental results represent that the diffusion of Zn in undoped InP deeply related to the equilibrium between interstitials and substitutional Zn is established via indium interstitials.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.5-6
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• 2009

In this paper, plasma ion implant is performed with $PH_3$ gas diluted by helium gas on P-type Si wafer (100). Spike Rapid Thermal Processing(RTP) annealing performed for 30~60 sec from $800\;^{\circ}C$ to $1000\;^{\circ}C$ in $N_2+O_2$ ambient. Crystalline defect is analyzed by Transmission Electron Microscope(TEM) and Double crystal X-ray Diffraction(DXRD). Contact resistivity($\rho c$), contact resistance(Rc) and sheet resistance(Rs) are analyzed by measuring Transfer Length Method(TLM) using 4155C analysis. As annealing temperature increase, Rs decrease and ${\rho}c$ and Rc increase at temperature higher than $850\;^{\circ}C$. We achieve low Rs, ${\rho}c$ and Rc with Plasma ion implant and spike RTP.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.583-586
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• 2011

In this paper, subthreshold swing characteristics have been presented for double-gate MOSFETs, using the analytical model based on series form of potential distribution. Subthreshold swing is very important factor for digital devices because of determination of ON and OFF. In general, subthreshold swings have to be under 100mV/dec. The channel length $L_g$ is varied from 30nm to 100nm, and channel thickness $t_{si}$ from 15 to 20nm according to channel length, and oxide thickness 5nm to investigate subthreshold swing. The doping of channel is fixed with $10^{16}cm^{-3}$ p-type. The results show good agreement with numerical simulations, confirming this model.