• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• 대한전자공학회논문지
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• 제27권2호
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• pp.98-104
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• 1990

$P^+$형 다결정 실리콘 게이트와 n형 다결정 실리콘 게이트를 갖는 P채널 MOSFET를 제작하였다. 채널의 길이와 채널의 이온 주입 조건에 따라 SC-PMOSFET와 BC-PMOSFET의 transconductance 문턱저압저하 및 subthreshold 특성을 분석하였다. 측정된 소자의 특성으로 부터 SC-PMOSFET소자가 BC-PMOSFET 소자에 비하여 transconductance는 작으며 subthreshold 영역에서 누설전류도 작고 문턱 전압 저하및 DIBL영향이 작게 일어남을 알 수 있었다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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• pp.559-562
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• 2008

In this paper we propose a lock-in detection method for portable sensor systems and demonstrate with the portable detection module that has high sensitivity and robustness against the noise. The simple portable sensor module is manufactured using MCU(Micro Contorl Unit), OPAMP, MOSFET and a pair of infrared sensor. Manufactured sensor module is testified in the noisy environment caused by an external light and an white noise source. Without any type of band pass filters, we recover a signal of 33 $mV_{p-p}$ in 80 $mV_{p-p}$ white noise and get the DR(Dynamic Reserve) of 14 dB.

• 한국전기전자재료학회논문지
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• 제23권10호
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• pp.767-770
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• 2010

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.153-162
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• 2014

We show that carbon nanotube sensors with gold particles on the single-walled carbon nanotube (SWNT) network operate as Schottky barrier transistors, in which transistor action occurs primarily by varying the resistance of Au-SWNT junction rather than the channel conductance modulation. Transistor characteristics are calculated for the statistically simplified geometries, and the sensing mechanisms are analyzed by comparing the simulation results of the MOSFET model and Schottky junction model with the experimental data. We demonstrated that the semiconductor MOSFET effect cannot explain the experimental phenomena such as the very low limit of detection (LOD) and the logarithmic dependence of sensitivity to the DNA concentration. By building an asymmetric concentric-electrode model which consists of serially-connected segments of CNTFETs and Schottky diodes, we found that for a proper explanation of the experimental data, the work function shifts should be ~ 0.1 eV for 100 pM DNA concentration and ~ 0.4 eV for $100{\mu}M$.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.55-55
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• 2001

개의 N과 P채널 EEPROM을 이용하여 A/D 변환기를 설계하였다. 프로그래밍 모드에서 EEPROM의 선형적 저장능력을 관찰하기 위해 MOSIS의 1.2㎛ double-poly CMOS 공정을 이용하여 셀이 제작되었다. 그 결과 1.25V와 2V구간에서 10㎷ 미만의 오차 내에서 셀이 선형적으로 프로그램 되는 것을 보았다. 이러한 실험 결과를 이용하여 프로그램 가능한 A/D 변환기의 동작이 Hspice에서 시뮤레이션 되었으며, 그 결과 A/D 변환기가 37㎼의 전력을 소모하고 동작주파수는 333㎒ 정도인 것으로 관찰되었다.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1865-1869
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• 1990

N-Channel polysilicon MOSFETs (W/L=20/1.5, 3, 5.10\ulcorner) were fabricated using RTP (Rapid Thermal Processor) and hydrogen passivation. The N+ source, drain and gate were annealed and recrystallized using RTP at temperature of 1000\ulcorner-1100\ulcorner. But the active areas were not specially crystallized before growing the gate oxide. Without the hydrogen passivarion, excellent transistor characteristics (ON/OFF=5.10**6, S=85MV/DEC, IL=51pA/\ulcorner) were obtained for 1.5\ulcorner MOSFET. Also the transistor characteristics were improved by hydrogen passivation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1372-1373
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2012년도 춘계학술발표회 논문집
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• pp.154-155
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• 2012

In this work, we report the comprehensive study of performance enhancement of InGaAs n-MOSFET by plasma $PH_3$ p assivation. The calibrated plasma $PH_3$ passivation of the InGaA ssurface before CVD high-k dielectric deposition significantly improves interface quality, resulting in suppressed frequency dispersion in C-V, increase in drive-current with high electron mobility, and excellent thermal stability.