• Title/Summary/Keyword: p-MOS

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A New Analog Switch CMOS Charge Pump Circuit without Body Effect

  • Parnklang, Jirawath;Manusphrom, Ampual;Laowanichpong, Nut;Tongnoi, Narongchai
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.212-214
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    • 2005
  • The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

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Design of 3~10GHz UWB Frequency Synthesizer for MBOA System (MBOA용 3~10GHz UWB 주파수합성기의 설계)

  • Kim, Dong-Shik;Chai, Sang-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.134-139
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    • 2013
  • This paper describes design of a RF frequency synthesizer for the MBOA UWB systems with $0.13{\mu}m$ silicon CMOS technology. To generate effective clock signal of the MBOA novel technique which uses large scale multiplication in band of low frequency and small scale multiplication in band of high frequency has been used to reduce oscillation bandwidth of VCO. To get good performance of high speed and wide band operation characteristics a VCO using PMOS core structure and a frequency divider using super dynamic structure used in design of PLL circuit.

A Study on the Isolation of the Oil-degradation Microbes and Treatment Efficiency in the Oil Contaminated Soil with Peat Moss (유류오염토양에서 유류분해 미생물의 분리 및 peat moss를 이용한 오염토양 처리에 관한 연구)

  • Chun, Mi-Hee;Son, Hee-Jeong;Kim, Chul
    • Journal of Environmental Health Sciences
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    • v.33 no.5
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    • pp.462-469
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    • 2007
  • Isolation and application of oil-degradation microbes from the oil-contaminated soil and the determination of optimal operation conditions about the peat moss, the addition for the oil-biodegradation. After all experiments, we have acquired three important conclusions: First, we found out the 4 microbes, Pseudomonas fluorescens, Pseudomonas aeruinosa, Kurtia sp., Bacillus ceres, with excellent capability for the oil-degradation; Second, the optimal operating conditions of the peat moss for TPH treatment were pH $7{\sim}8$, temperature $25{\sim}30^{\circ}C$, water content 20%, mixing 2 times/ day, addition volume 2%; Third, in case of the application to the oil-contaminated soil with 4 mixed microbes, the removal efficiency of TPH was increased from 54% to 83% in oil-contaminated soil and from 65% to 85% in oil-contaminated soil with the peat moss.

Development of High Aperture Ratio 2.1” QVGA LTPS (Low Temperature Poly Si) LCD Using SLS (Sequential Lateral Solidification) Technology

  • Kang, Myung-Koo;Lee, Joong-Sun;Park, Jong-Hwa;Zhang, Lintao;Joo, Seung-Yong;Kim, Chul-Ho;Kim, Il-Kon;Kim, Sung-Ho;Park, Kyung-Soon;Yoo, Chun-Ki;Kim, Chi-Woo
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.1033-1034
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    • 2005
  • High resolution 2.1” QVGA LTPS LCD (190ppi) having high aperture ratio of 65% could be successfully developed using state-of-the-art SLS technology and active/gate storage structure. Cost effective P-MOS 6-Mask structure was used. Full gate and transmission gate circuits are integrated in the panel. The high aperture ratio was obtained by using active/gate capacitance structure, which can reduce storage capacitance area. The aperture ratio was increased to 65% from 49% of conventional gate/data capacitance structure. The brightness was increased from 180cd to 270cd without any degradation of optical properties such as contrast ratio, flicker or crosstalk.

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Analytical Modeling for Short-Channel MOSFET I-V Characteristice Using a Linearly-Graded Depletion Edge Approximation (공핍층 폭의 선형 변화를 가정한 단채널 MOSFET I-V 특성의 해석적 모형화)

  • 심재훈;임행삼;박봉임;여정하
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.4
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    • pp.77-85
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    • 1999
  • By assuming a linearly graded depletion edge approximation in the intrinsic MOS region and by taking into account the mobility variation dependent on both lateral and vertical fields, a physics-based analytical model for a short-channel(n-channel) MOSFET is suggested. Derived expressions for the threshold voltage and the drain current of typical MOSFET is structures could be used in a unified manner for all operating range. The threshold voltage was calculated by changing following variables : channel length, drain-source voltage, source-substrate voltage, p-substrate doping level, and oxide thickness. It is shown that the threshold voltage decreases almost exponentially as the channel length decreases. In addition, the short-channel threshold voltage roll-off, the channel length modulation and the electron mobility degradation can be derived within a satisfactory accuracy.

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Memory Characteristics of High Density Self-assembled FePt Nano-dots Floating Gate with High-k $Al_2O_3$ Blocking Oxide

  • Lee, Gae-Hun;Lee, Jung-Min;Yang, Hyung-Jun;Kim, Kyoung-Rok;Song, Yun-Heub
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.388-388
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    • 2012
  • In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

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A Triple-Band Voltage-Controlled Oscillator Using Two Shunt Right-Handed 4th-Order Resonators

  • Lai, Wen-Cheng;Jang, Sheng-Lyang;Liu, Yi-You;Juang, Miin-Horng
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.506-510
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    • 2016
  • A triple-band (TB) oscillator was implemented in the TSMC $0.18{\mu}m$ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt $4^{th}$ order LC resonators to form a $6^{th}$ order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) mA and 2.4(2.29, 2.28) mW, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 GHz, 5.82-6.15 GHz, and 3.68-4.08 GHz. The die area of the triple-band oscillator is $0.835{\times}1.103mm^2$.

Modeling and Simulation on Ion Implanted and Annealed Indium Distribution in Silicon Using Low Energy Bombardment (낮은 에너지로 실리콘에 이온 주입된 분포와 열처리된 인듐의 거동에 관한 시뮬레이션과 모델링)

  • Jung, Won-Chae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.29 no.12
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    • pp.750-758
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    • 2016
  • For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

A SPICE-Compatible Model for a Gate/Body-Tied PMOSFET Photodetector With an Overlapping Control Gate

  • Jo, Sung-Hyun;Bae, Myunghan;Choi, Byoung-Soo;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.24 no.5
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    • pp.353-357
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    • 2015
  • A new SPICE-compatible model for a gate/body-tied PMOSFET photodetector (GBT PD) with an overlapping control gate is presented. The proposed SPICE-compatible model of a GBT PD with an overlapping control gate makes it possible to control the photocurrent. Research into GBT PD modeling was proposed previously. However, the analysis and simulation of GBT PDs is not lacking. This SPICE model concurs with the measurement results, and it is simpler than previous models. The general GBT PD model is a hybrid device composed of a MOSFET, a lateral bipolar junction transistor (BJT), and a vertical BJT. Conventional SPICE models are based on complete depletion approximation, which is more applicable to reverse-biased p-n junctions; therefore, they are not appropriate for simulating circuits that are implemented with a GBT PD with an overlapping control gate. The GBT PD with an overlapping control gate can control the sensitivity of the photodetector. The proposed sensor is fabricated using a $0.35{\mu}m$ two-poly, four-metal standard complementary MOS (CMOS) process, and its characteristics are evaluated.

A Study on Effect of Self-management and Self-resiliency on Career Maturity in University Students (대학생의 자기관리와 자아탄력성이 진로성숙도에 미치는 영향)

  • Yoo, Seung-Ok
    • Journal of Korea Entertainment Industry Association
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    • v.15 no.5
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    • pp.153-161
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    • 2021
  • The purpose of this study was to provide effective career coaching method to help university students to choose suitable career in transition to society. The subjects were 250 students enrolled in G University and questionnaire survey was administerd. The collected data were analyzed using SPSS v. 21.0 statistics package program and the results are as follows: For the general characteristics of subjects, female students were more compared to male ones, mos of them were in 4th grade and specialized in public health and had no religion. For the relationship between self-management / self-resiliency and career maturity of university students, the self-management had significant positive effects on determination, confidence, and preparedness, which are sub-factors of career maturity (p<.001). In addition, it was shown that the controllability, positiveness, and sociability, which are sub-factors of self-resiliency had significant positive effects on determination, confidence, and preparedness, which are sub-factors of career maturity (p<.05, p<.01, p<.001). Considering that the self-management and self-resiliency are important factors in career maturity of university students, it is demanded for the university teachers to examine the measures to increase self-management and self-resiliency of students.