• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.113-121
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• 1993

In the formation of the shallow p$^{+}$-n junction, the preamorphization method by As$^{+}$ ions was applied in order to avoid the boron channeling effect which is occured during the B$^{+}$ implantation especially with low energy. By As$^{+}$ pre-implant with 60KeV energy and 2*10$^{14}$ cm$^{-2}$ dose, the channelinf of B$^{+}$ ions implanted with 10keV/1.5*10$^{14}$ cm$^{-2}$ can be avoded completely. After the RTA of 1050.deg. C and 10sec, the junction depth was 0.14.mu.m, the leakage current was 20nA/cm$^{2}$(at-5V bias) and the sheet resistance was 107.OMEGA./ㅁ. And the preamorphized Si layer was changed into the perfect crystal si after the RTA.r the RTA.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.867-870
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• 1998

In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.772-777
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• 2018

This paper used RF Magnetron Sputtering to deposition n-type and p-type to ITO glass. The N-type ohmic contact worked well under all conditions. Sheet resistance has been shown to increase sheet resistance as RF Power increases. After analyzing the surface of the deposited thin film, in the condition that RF Power was 250W and substrate temperature was $250^{\circ}C$, particles were measured to have a uniform and consistent thin film. P-type has good ohmic contact under all conditions and sheet resistance has been shown to increase as RF Power increases. As the RF Power grew, thickness increased and stabilized. PN junction thin film and NP junction thin film showed increased thickness and stabilized as sputtering time increased. As a result of thin film, conversion efficiency was at 0.2 when sputtering time was 10 minutes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.348-349
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• 2007

This paper describes the electrical characteristics of polycrystalline (poly) 3C-SiC thin film diodes, in which poly 3C-SiC thin films on n-type and p-type Si wafers, respectively, were deposited by APCVD using HMDS, Hz, and Ar gas at $1180^{\circ}C$ for 3 hr. The schottky diode with Au/poly 3C-SiC/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) values were measured as 0.84 V, over 140 V, 61nm, and $2.7\;{\times}\;10^{19}\;cm^3$, respectively. The p-n junction diodes fabricated on the poly 3C-SiC/Si(p-type) were obtained like characteristics of single 3C-SiC p-n junction diodes. Therefore, poly 3C-SiC thin film diodes will be suitable microsensors in conjunction with Si fabrication technology.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.65-71
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• 1997

We present heterojunction solar cells with a structure of metal/a-Si:H(n-i-p)/poly-Si(n-p)/metal for the terrestrial applications. This cell consists fo two component cells: a top n-i-p junction a-Si:Hi cell with wide-bandgap 1.8eV and a bottom n-p junction poly-Si cell with narrow-bandgap 1.1eV. The efficiency influencing factors of the solar cell were investigated in terms of simulation an experiment. Three main topics of the investigated study were the bottom cell with n-p junction poly-Si, the top a-Si:H cell with n-i-p junction, and the interface layer effects of heterojunction cell. The efficiency of bottom cell was improved with a pretreatment temperature of 900$^{\circ}C$, surface polishing, emitter thickness of 0.43$\mu\textrm{m}$, top Yb metal, and grid finger shading of 7% coverage. The process optimized cell showed a conversion efficiency about 16%. Top cell was grown by suing a photo-CVD system which gave an ion damage free and good p/i-a-Si:H layer interface. The heterojunction interface effect was examined with three different surface states; a chemical passivation, thermal oxide passivation, and Yb metal. the oxide passivated cell exhibited the higher photocurrent generation and better spectral response.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.38-48
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• 1993

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.152-153
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• 1994

A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.144.1-144.1
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• 2016

We fabricate organic single crystal nanowire heterojunction p-n diode poly(3-hexylthiophene)(P3HT) and from Phenyl-C61-butyric acid methyl ester(PCBM) using by liquid-bridge mediated nanotransfer molding(LB-nTM) method. LB-nTM has been reported an one step direct printing method for making well-aligned nanowire arrays. Moreover, multi-patterning nanostructures can be fabricated with the consecutive printing process. As a result, it is possible to make simple and basic concept of heterojunction devices such as lateral organic p-n nanojunction diode. P3HT/PCBM nanowires heterojunction diode has rectifying behavior with on/off ratios of ~20.

• Solar Energy
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• v.11 no.3
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• pp.74-83
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• 1991

In this study, the (p)ZnTe/(n)Si solar cell and (n)CdS-(p)ZnTe/(n)Si poly-junction thin film are fabricated by vaccum deposition method at the substrate temperature of $200{\pm}1^{\circ}C$ and then their electrical properties are investigated and compared each other. The test results from the (p)ZnTe/(n)Si solar cell the (n)CdS-(p)ZnTe/(n)Si poly-junction thin fiim under the irradiation of solar energy $100[mW/cm^2]$ are as follows; Short circuit current$[mA/cm^2]$ (p)ZnTe/(n)Si:28 (n)CdS-(p)ZnTe/(n)Si:6.5 Open circuit voltage[mV] (p)ZnTe/(n)Si:450 (n)CdS-(p)ZnTe/(n)Si:250 Fill factor (p)ZnTe/(n)Si:0.65 (n)CdS-(p)ZnTe/(n)Si:0.27 Efficiency[%] (p)ZnTe/(n)Si:8.19 (n)CdS-(p)ZnTe/(n)Si:2.3 The thin film characteristics can be improved by annealing. But the (p)ZnTe/(n)Si solar cell are deteriorated at temperatures above $470^{\circ}C$ for annealing time longer than 15[min] and the (n)CdS-(p)ZnTe/(n)Si thin film are deteriorated at temperature about $580^{\circ}C$ for longer than 15[min]. It is found that the sheet resistance decreases with the increase of annealing temperature.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.134-142
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• 1996

The epi-CoSi$_{2}$ layer was formed by alloying a Co(120$\AA$)/Ti(50$\AA$) bilayer. In addition, the ultra shallow p$^{+}$n junction of which depth is about not more than 40nm at the background concentration, 10$^{18}$atoms/cm$^{3}$ could be formed by annealing (RTA-II) the ion implanted epi-silicide. When the temperature of RTA-I is as low as possible and that of RTA-II is moderate, the p$^{+}$n junction that has low leakage current and stable epi-silicide layer could be obtained. That is, when th econdition of TRA-I was 900$^{\circ}C$/20sec and that of RTA-II was 900$^{\circ}C$/10sec, the reverse leakage current was as high as 11.3$\mu$A/cm$^{2}$ at -5V. The surface of CoSi$_{2}$ appeared considerably rough. However, when the conditon of RTA-I was 800$^{\circ}C$/20sec or 700$^{\circ}C$/20sec, the leakage currents were as low as 8.3nA/cm$^{2}$ and 9.3nA/cm$^{2}$, respectively and also the surfaces appeared very uniform.