• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.473-478
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• 2016

In this paper, the MIS(: Metal-Insulator-Semiconductor) Capacitor with the nitrided-oxide by RTP are fabricated to investigate the carrier trap parameters due to avalanche electron injection. Two times turn-around phenomenon of the flatband voltage shift generated by the avalanche injection are observed. This shows that electron trapping occurs in the oxide film at the first stage. As the electron injection increases, the first turn-around occures due to a positive charge in the oxide layer. After further injection, the curves turns around once again by electron captured. Based on the experimental results, the carrier trapping model for system having multi-traps is proposed and is fitting with experimental data in order to determine trap parameter of nitrided-oxide.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.1-8
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• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.102-105
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• 1997

The thickness dependence of stress voltage oxide currents has been measured in oxides with thicknesses between 10nm and 80nm. The oxide currents were shown to be composed of stress current and transient current. The stress current was caused by trap assited tunneling through the oxide. The transient current was caused by the tunneling charging and discharging of the trap in the interfaces. The stress current was used to estimate to the limitations on oxide thicknesses. The transient current was used to the data retention in memory devices.

• Transactions on Electrical and Electronic Materials
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• v.4 no.6
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.43-49
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• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.461-464
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• 1999

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$ to 814$\AA$ with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ . The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• Journal of IKEEE
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• v.27 no.3
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• pp.303-307
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• 2023

In this paper, the creation of an Electron-Hole Pair due to Total Ionizing Dose (TID) effects inside the oxide of a Buried Channel Array Transistor (BCAT) device is induced, resulting in an increase in leakage current and threshold due to an increase in hole trap charge at the oxide interface. By comparing and simulating changes in voltage with the previously proposed Partial Isolation Buried Channel Array Transistor (Pi-BCAT) structure, the characteristics in leakage current and threshold voltage changed regardless of the increased oxide area of the Pi-BCAT device, compared to the asymmetrically doped BCAT structure. It shows superiority.

• Journal of the Korean Ceramic Society
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• v.31 no.5
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• pp.529-537
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• 1994

The principle of the Isothermal Capacitance Transient Spectroscopy[ICTS] were explained to measure the electronic trap levels in oxide ceramics. The measurement apparatus and the theory of the ICTS were described in detail. The trap energy evaluation was performed for the ZnO varistor and BaTiO3 ceramics. The grain boundary interface trap levels were detected at -5$0^{\circ}C$~6$0^{\circ}C$ in the case of ZnO varistor and PTCR samples, and the bulk trap levels were detected at 2$0^{\circ}C$~60~ in BaTiO3. The trap energy levels of the above samples could be directly determined by ICTS measurement.