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A Study on the Efficiency of Join Operation On Stream Data Using Sliding Windows (스트림 데이터에서 슬라이딩 윈도우를 사용한 조인 연산의 효율에 관한 연구)

  • Yang, Young-Hyoo
    • Journal of the Korea Society of Computer and Information
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    • v.17 no.2
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    • pp.149-157
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    • 2012
  • In this thesis, the problem of computing approximate answers to continuous sliding-window joins over data streams when the available memory may be insufficient to keep the entire join state. One approximation scenario is to provide a maximum subset of the result, with the objective of losing as few result tuples as possible. An alternative scenario is to provide a random sample of the join result, e.g., if the output of the join is being aggregated. It is shown formally that neither approximation can be addressed effectively for a sliding-window join of arbitrary input streams. Previous work has addressed only the maximum-subset problem, and has implicitly used a frequency based model of stream arrival. There exists a sampling problem for this model. More importantly, it is shown that a broad class of applications for which an age-based model of stream arrival is more appropriate, and both approximation scenarios under this new model are addressed. Finally, for the case of multiple joins being executed with an overall memory constraint, an algorithm for memory allocation across the join that optimizes a combined measure of approximation in all scenarios considered is provided.

Discharge Patterns and Peripheral Nerve Inputs to Cardiovascular Neurons in the Medulla of Cats: Comparison between the lateral and medial medulla

  • Kim, Sang-Jeong;Lim, Won-Il;Park, Myoung-Kyu;Lee, Jin;Kim, Jun
    • The Korean Journal of Physiology
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    • v.28 no.2
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    • pp.133-141
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    • 1994
  • The discharge patterns and peripheral nerve inputs to cardiovascular neurons were investigated in rostral ventrolateral medulla (RVLM) and raphe nucleus of cats. The data from the two were compared to determine their roles in cardiovascular regulation and the endogenous analgesic system. Animals were anesthetized with ${\alpha}-chloralose$ and single cell activities were recorded by carbon-filament microelectrode and their relationships with cardiovascular activity were analyzed. In RVLM area, a total of thirty-three cells were identified as cardiovascular neurons. During one cardiac cycle, the mean discharge rate of the neurons was $1.96{\pm}0.29$ and the peak activity was observed 45 ms after the systolic peak of arterial blood pressure. Thirteen cells could be activated antidromically by stimulation of the the $T_2$ intermediolateral nucleus. Forty-three raphe neurons were identified as cardiovascular neurons whose mean discharge rate during one cardiac cycle was $1.02{\pm}0.12$. None of these cells could be activated antidromically. Study of the interval time histogram of RVLM neurons revealed that the time to the first peak was $128{\pm}20.0\;ms$, being shorter than the period of a cardiac cycle. The same parameter found from the raphe neurons was $481{\pm}67.2\;ms$, which was much longer than the cardiac cycle length. Of seventeen RVLM neurons examined ten received only the peripheral $A{\delta}-afferent$ inputs, whereas six RVLM neurons received both $A{\delta}-$ and C-inputs; the remaining one cell received an inhibitory peripheral C-input. In contrast, nine of eleven raphe neurons were found to receive $A{\delta}-inputs$ only. We conclude that the main output of cardiovascular regulatory influences are mediated through the RVLM neurons. The cardiovascular neurons in the raphe nucleus appear to serve as interneurons transferring cardiovascular afferent information to the raphespinal neurons mediating the endogenous analgesic mechanisms.

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Design of a Hybrid Fuzzy Controller for Speed Control of a Hydraulic Elevator Controlled by Inverters (유압식 인버터 엘리베이터의 속도제어를 위한 하이브리드 퍼지제어기의 설계)

  • Han, Gueon-Sang;Kim, Byoung-Hwa;Ahn, Hyun-Sik;Kim, Do-Hyun
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.38 no.1
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    • pp.1-13
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    • 2001
  • Due to the friction characteristics of cylinders and the rail of a passenger car, in the elevator actuated with hydraulic systems, there exist dead zones, which can not be controlled by a PID controller. To overcome the drawbacks, in this paper, we first try a hybrid controller which switches between a fuzzy logic controller and a PID controller. However, because the hybrid control scheme uses only a single type controller, except the switched layer, the high control performance can not be achieved. To solve this problem, we propose a new type fuzzy hybrid control scheme, which outputs of the output mixer arc controlled by a fuzzy logic. The hydraulic elevator system controlled by inverters has more then one switched layers due to the highly nonlinear characteristics. The proposed fuzzy hybrid control scheme achieves improved control performances by using both controllers with weighted outputs depend on the system status, to achieve improved control performances. The effectiveness of the proposed control scheme arc shown by simulation results, which the proposed fuzzy hybrid control method yields good control performance not only in the zero crossing speed region but also in the overall control region including steady-state region.

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Design of Carrier Recovery Circuit for High-Order QAM - Part I : Design and Analysis of Phase Detector with Large Frequency Acquisition Range (High-Order QAM에 적합한 반송파 동기회로 설계 - I부. 넓은 주파수 포착범위를 가지는 위상검출기 설계 및 분석)

  • Kim, Ki-Yun;Cho, Byung-Hak;Choi, Hyung-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.4
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    • pp.11-17
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    • 2001
  • In this paper, we propose a polarity decision carrier recovery algorithm for high order QAM(Quadrature Amplitude Modulation), which has robust and large frequency acquisition performance in the high order QAM modem. The proposed polarity decision PD(Phase Detector) output and its variance characteristic are mathematically derived and the simulation results are compared with conventional DD(Decision-Directed) method. While the conventional DD algorithm has linear range of $3.5^{\circ}{\sim}3.5^{\circ}$, the proposed polarity decision PD algorithm has linear range as large as $-36^{\circ}{\sim}36^{\circ}$ at ${\gamma}-17.9$. The conventional DD algorithm can only acquire offsets less than ${\pm}10\;KHz$ in the case of the 256 QAM while an analog front-end circuit generally can reduce the carrier-frequency offset down to only ${\pm}100\;KHz$. Thus, in this case additional AFC or phase detection circuit for carrier recovery is required. But by adopting the proposed polarity decision algorithm, we can find the system can acquire up to ${\pm}300\;KHz$at SNR = 30dB without aided circuit.

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New Beamforming Schemes with Optimum Receive Combining for Multiuser MIMO Downlink Channels (다중사용자 다중입출력 하향링크 시스템을 위한 최적 수신 결합을 이용한 새로운 빔 형성 기법)

  • Lee, Sang-Rim;Park, Seok-Hwan;Moon, Sung-Hyun;Lee, In-Kyu
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.8
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    • pp.15-26
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    • 2011
  • In this paper, we present a new beamforming scheme for a downlink of multiuser multiple-input multipleoutput (MIMO) communication systems. Recently, a block-diagonalization (BD) algorithm has been proposed for the multiuser MIMO downlink where both a base station and each user have multiple antennas. However, the BD algorithm is not efficient when the number of supported streams per user is smaller than that of receive antennas. Since the BD method utilizes the space based on the channel matrix without considering the receive combining, the degree of freedom for beamforming cannot be fully exploited at the transmitter. In this paper, we optimize the receive beamforming vector under a zero forcing (ZF) constraint, where all inter-user interference is driven to zero. We propose an efficient algorithm to find the optimum receive vector by an iterative procedure. The proposed algorithm requires two phase values feedforward information for the receive combining vector. Also, we present another algorithm which needs only one phase value by using a decomposition of the complex general unitary matrix. Simulation results show that the proposed beamforming scheme outperforms the conventional BD algorithm in terms of error probability and obtains the diversity enhancement by utilizing the degree of freedom at the base station.

The Solution of Content Creation for User Side Using Animation Management System (애니메이션 공정관리시스템을 활용한 사용자 중심 콘텐츠 생성 방안)

  • Lim, Yang-Mi;Kim, Sung-Rea;Kim, Ho-Sung
    • Proceedings of the Korea Contents Association Conference
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    • 2006.11a
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    • pp.163-167
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    • 2006
  • The previous media has the function that was information of the contents was delivered by only content providers, but the current media makes the interactive function between content providers and general receivers. For this reason, the role of receivers are also expanded in the realm of multimedia and receivers have the roles of the sending and getting information for content user, not more receiver. The constituent members relative to content are content providers, users and user-created content. This paper introduces "the wonderland" the animation process management system for high-level user group. Also, most of images which are made of the animation process are publicly accessible, providing the public or the average user group for making resources easily by using "the wonderland." Although, the general user can get an environment to reedit their own new movie with making the most of provided movie sources are scene and cut units, according to one's taste and one's idea. The materialization of process management system can expand dramatically enough contents, and save the time to edit digital animation or movie, control numerous sources, made an animation processing, and the result output. Such "the wonderland" will significantly help to create future content.

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Hierarchical Recognition of English Calling Card by Using Multiresolution Images and Enhanced RBF Network (다해상도 영상과 개선된 RBF 네트워크를 이용한 계층적 영문 명함 인식)

  • Kim, Kwang-Baek;Kim, Young-Ju
    • The KIPS Transactions:PartB
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    • v.10B no.4
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    • pp.443-450
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    • 2003
  • In this paper, we proposed the novel hierarchical algorithm for the recognition of English calling cards that processes multiresolution images of calling cards hierarchically to extract individual characters and recognizes the extracted characters by using the enhanced neural network method. The hierarchical recognition algorithm generates multiresolution images of calling cards, and each processing step in the algorithm selects and processes the image with suitable resolution for lower processing overhead and improved output. That is, first, the image of 1/3 times resolution, to which the horizontal smearing method is applied, is used to extract the areas including only characters from the calling card image, and next, by applying the vertical smearing and the contour tracking masking, the image of a half time resolution is used to extract individual characters from the character string areas. Lastly, the original image is used in the recognition step, because the image includes the morphological information of characters accurately. And for the recognition of characters with diverse font types and various sizes, the enhanced RBF network that improves the middle layer based on the ART1 was proposed and applied. The results of experiments on a large number of calling card images showed that the proposed algorithm is greatly improved in the performance of character extraction and recognition compared with the traditional recognition algorithms.

Performance Evaluation of Networks with Buffered Switches (버퍼를 장착한 스위치로 구성된 네트워크들의 성능분석)

  • Shin, Tae-Zi;Nam, Chang-Woo;Yang, Myung-Kook
    • Journal of KIISE:Information Networking
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    • v.34 no.3
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    • pp.203-217
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    • 2007
  • In this paper, a performance evaluation model of Networks with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch networks. The characteristic of a network with crossbar switches is determined by both the connection pattern of the switches and the limitation of data flow in a each switch. In this thesis, the evaluation models of three different networks : Multistage interconnection network, Fat-tree network, and other ordinary communication network are developed. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of networks that uses the multiple buffered crossbar switches. It is shown that both the analysis and the simulation results match closely. It is also observed that the increasing rate of Normalized Throughput is reduced and the Network Delay is getting bigger as the buffer size increased.

A practial design of direct digital frequency synthesizer with multi-ROM configuration (병렬 구조의 직접 디지털 주파수 합성기의 설계)

  • 이종선;김대용;유영갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.12
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    • pp.3235-3245
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    • 1996
  • A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

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Design of a Novel Instrumentation Amplifier using Current-conveyor(CCII) (전류-컨베이어(CCII)를 사용한 새로운 계측 증폭기 설계)

  • CHA, Hyeong-Woo;Jeong, Tae-Yun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.12
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    • pp.80-87
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    • 2013
  • A novel instrumentation amplifier(IA) using positive polarity current-conveyor(CCII+) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of two CCII+, three resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into two CCII+ used voltage and current follower converts into same currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the CCII+ and used commercial op-amp LF356. Simulation results show that voltage follower used CCII+ has offset voltage of 0.21mV at linear range of ${\pm}$4V. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the gain of 60dB was 400kHz. The IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 130mW at supply voltage of ${\pm}$5V.