• 전기전자학회논문지
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• 제19권4호
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• pp.465-471
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• 2015

An LC-tuned sinusoidal voltage-controlled oscillator (VCO) using temperature-stable linear operational transconductance amplifiers (OTAs) is presented. Its architecture is based on Hartley oscillator configuration, where the inductor is active one realized with two OTAs and a grounded capacitor. Two diode limiters are used for limiting amplitude. A prototype oscillator built with discrete components exhibits less than 3.1% nonlinearity in its current-to-frequency transfer characteristic from 1.99 MHz to 39.14 MHz and $220ppm/^{\circ}C$ frequency stability to the temperature drift over 0 to $75^{\circ}C$. The total harmonic distortion (THD) is as low as 4.4 % for a specified frequency-tuning range. The simulated phase noise of the VCO is about -108.9 dBc/Hz at 1 MHz offset frequency in frequency range of 0.4 - 46.97 MHz and property of phase noise of VCO is better than colpitts-VCO.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.113-116
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• 2000

Phase noise of oscillator gives the performance degradation significantly when a high carrier frequency and low transmission rate are used. The BER(Bit Error Rates) degradation of QPSK(Quadrature Phase Shift Keying) transmission is analyzed with the oscillator phase noise level specified in downstream physical interface of LMDS(Local Multipoint Distribution Services) which is described in DAVIC(Digital Audio Visual Council). The model used for the phase noise is a power-law model. We also investigated the effects of the various transmission rates on system performance. For the transmission rate below 0.5 Mbps, the BER performance is severely degraded and we verified that the transmission rate, 20 Mbps, is adequate for the downstream of LMDS systems.

• 한국통신학회논문지
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• 제21권12호
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• pp.3215-3226
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• 1996

In this paper a K-band harmonic oscillator competitive to ordinary Push-Push type oscillators is introduced. This oscillator is composed of two-X-band dielectric resonance circuits. To favor its harmonic generation, the load effect and the bias effect are studied to allow the maximum harmonic distortion. As results, the dielectric resonated load and the class A bias are used for the 2nd harmonic generation. analytical study for modelling of voltage controlled dielectric resonator is carried out with theoretical background. The performance of the circuit is evaluated by simulation using harmonic balanced method. The novel structure has ont only a voltage tuning circuit but also an output port at fundamental frequency as the function of prescaler for phase lockede loop application on the just single oscillation structure. In experimentation, the output freqneyc of the 2nd harmonic signal is 20.5GHz and the maximum power level of output is +5.5dBm without additional post amplifiers. the harmonic oscillator exhibits -30dBc of high fundamental frequency rejection without added extra filters. The phase noise of -90dBc/Hz at 100kHz off-carrier has been achieved under free running condition, that satisfies phase noise requirement of IESS 308. The proposed oscillator may be utilized as the clean and stable fixed local oscillator in Transmit Block Upconvertor(TBU) or Low oise Block downconvertor(LNB) for K/Ka-band digital communications and satellite broadcastings.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.479-481
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• 2006

This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.

• 한국정보통신학회논문지
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• 제16권12호
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• pp.2589-2594
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• 2012

평면형 마이크로스트립 공진기를 이용한 고주파 발진기의 단점인 위상잡음 특성을 개선하기 위해 본 논문에서는 링형 DGS 공진기를 제안하고, 이것을 이용하여 위상잡음 특성이 개선된 5.8 GHz 대역의 발진기를 설계, 구현하였다. 링형 DGS 공진기는 $50{\Omega}$ 전송선로 밑면에 링 모양으로 식각된 접지면을 갖는 구조이다. 발진기의 특성은 5.8 GHz 기본 주파수에서 6.1 dBm의 출력과 -82.7 dBc@100kHz의 위상잡음 특성을 나타내었다. 제안된 DGS 공진기의 에칭된 갭 사이에 버랙터 다이오드 실장하여 전압제어 발진기를 설계하였다. 본 논문의 발진기는 평면형 구조로 쉬운 작업공정과 소형화 특성 때문에 MIC 또는 MMIC 분야의 발진기 설계에 응용될 수 있을 것이다.

• 한국전자파학회논문지
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• 제13권1호
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• pp.74-79
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• 2002

본 논문에서는 Ka-band 위성 중계기용 국부 발진기에 사용하게 될 전압제어 발진기의 EM(Engineering Model)을 비선형 방법으로 설계하였다. 전압제어 발진기의 위상잡음을 개선하기 위하여 공진기로 사용되는 유전체 공진기와 결합하는 마이크로스트립 라인을 high impedance inverter로 구현함으로써 공진회로의 quality factor를 우수하게 유지하여 능동소자에 전달되도록 하였다. 개발된 전압제어 발진기는 0~12 V의 제어전압으로 9.7965~9.8032 GHz의 튜닝범위를 가지며 공급전력은 8V, 17mA를 필요로 한다. 제작된 전압제어 발진기의 위상잡음은 -96.51 dBc/Hz ⓐ10 KHz와 -116.5 dBc/Hz ⓐ100 KHz의 특성을 나타내며 출력전력은 7.33 dBm을 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.42-47
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• 2017

This paper proposes a new series-coupled voltage-controlled oscillator (VCO). The proposed VCO consists of four current-reuse Armstrong VCOs (CRA-VCOs) coupled by four transformers. The series-coupling, current-reuse, and Armstrong topologies improve the phase noise performance by increasing the negative-Gm of the VCO core with half the current consumption of a conventional differential VCO. The proposed VCO consumes 6.54 mW at 9.78 GHz from a 1-V supply voltage. The measured phase noise is -115.1 dBc/Hz at an offset frequency of 1 MHz, and the FoM is -186.5 dBc/Hz. The frequency tuning range is from 9.38-10.52 GHz. The core area is $0.49mm^2$ in a $0.13-{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.207-212
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• 2013

A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.

• 한국전자파학회논문지
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• 제25권5호
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• pp.515-525
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• 2014

본 논문에서는 저 위상잡음을 갖는 전압 제어 평판형 복합공진기 발진기(Vt-PCRO: Voltage-tuned Planar Composite Resonator Oscillator)를 설계, 제작하였다. 설계된 발진기는 공진기, 2개의 위상천이기, 증폭기로 구성된다. 공진기는 dual mode SIW(Substrate Integrated Waveguide) 공진기를 이용하여 구성하였으며, 약 40 nsec의 높은 군지연을 갖도록 하였다. 2개의 위상천이기 중(PS1, PS2: Phase Shifter 1 및 Phase Shifter 2) PS1은 $360^{\circ}$의 위상천이량을 가지며, 제작된 발진기의 전송선로 길이에 관계없이 개루프 이득(open loop gain) 발진조건을 만족하도록 한다. PS2는 약 $70^{\circ}$의 위상천이량을 가지며 발진 주파수 조정용으로 사용된다. 증폭기는 제작 시 발생한 큰 삽입손실의 문제를 보완하기 위해 2단으로 구성하였다. 개루프 이득 측정을 통해 발진 조건을 만족하는 PS1의 전압을 측정한 뒤, 폐루프로 구성하여 발진기를 구현하였다. 발진기 측정 결과, 5.345 GHz의 발진 주파수에서, 위상 잡음은 100 kHz offset 주파수에서 -130.5 dBc/Hz를 얻었다. 이때 출력 전력은 약 3.5 dBm, 전기적 주파수 조정 범위는 0~10 V의 조정 전압에서 약 4.2 MHz를 보였다.

• 한국ITS학회:학술대회논문집
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• 한국ITS학회 2006년도 제5회 추계학술대회 및 정기총회
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• pp.316-320
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• 2006