• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.1
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• pp.94-99
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• 1997

There are several factors that have influence on the phase noise of an oscillator. But one of the major factors is the flicker noise of a transistor, since the phase noise of an oscillator is generated by mixing the carrier with the low frequency noise near the DC having the characteristic of 1/f. In this paper, we have presented a method on reducing the phase noise of an oscillator by using a low-frequency feedback circuit based on an active bias circuit, and have fabricated a DRO for a DBS receiver. Measurement results show that the phase noise is -92 dBc/Hz at the 10 KHz offset frequency, and from these results we have found out that the reduction method is very effective.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.441-446
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• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.5
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• pp.89-96
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• 2012

In this paper, a low phase noise oscillator is designed using an interdigital hairpin resonator for UTIS (Urban Traffic Information Systems). The interdigital hairpin resonator has several characteristics compared with a conventional hairpin resonator, which are 70% size reduction and improvement of harmonic characteristics. In addition, Q (Quality factor) of the interdigital hairpin resonator is about 132, which is suitable for the design of a low phase noise oscillator. The oscillator suggested in this paper shows the output power of 12 dBm and the phase noise characteristic of -100.8 dBc/Hz at 100 kHz offset frequency from the center frequency of 5.75 GHz. The phase noise is improved by about 12 dB compared with a conventional oscillator using an interdigital hairpin resonator.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.359-365
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• 2016

In this paper, a novel coupled C type resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator. Oscillator using proposed coupled C type resonator is designed, it has improved phase noise characteristics. At the fundamental frequency of 9.8GHz, 2.4dBm output power and -82.7 dBc@100kHz phase noise have been measured for oscillator with coupled C type resonator. The phase noise characteristics of oscillator is improved about 9.7dB compared to one using the general ${\lambda}/4$ microstrip resonator. Due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we analysed coupling coefficient between dielectric resonator of high dielectric constant and microstrip line to design for low phase noise dielectric resonator by direct coupling. Also we analysed phase noise of dielectric resonance oscillator with parallel feedback circuit to complement Q by high dielectric constant. We obtained a result from high-stability dielectric oscillator which is optimum designed through analysis of dielectric resonance oscillator phase noise and coupling coefficient. The result is that the phase noise was -83.3dBc/Hz@1KHz at 20.25GHz when we used about 3.6 coupling coefficient and ${\epsilon}_r$=30 dielectric resonator of 20.25GHz dielectric resonance oscillator. As a result, we suggested the direct-connect design method by frequency multiplication mode to prevent phase noise loss at K-Band.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.174-177
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• 2009

In this paper, an oscillator using dielectric-rod loaded cavity resonators with HTS(High Temperature Superconductor) end-plates was presented. It was operated at X-band. A two port cavity resonator was incorporated into a basic feedback loop oscillator configuration. A rutile loaded cavity resonator with HTS thin film end-plates was used to provide the quality factor between $10^4$ and $10^6$. A parallel feedback oscillator was constructed with a dielectric loaded cavity resonator, an amplifier, and a directional coupler. At 300 K, the experimental results showed the phase noise of -108 dBc/Hz at a 100 kHz offset frequency. At 26 K, the results was -118.8 dBc/Hz at same offset frequency.

• Journal of electromagnetic engineering and science
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• v.16 no.3
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• pp.191-193
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• 2016

This paper proposes a voltage-controlled oscillator (VCO) that has broadband turning and low-level of phase noise characteristics. Due to the micro-strip line resonant circuit with a low Q value, which is applied to the broadband tuning range, the depreciated phase noise performance is compensated by restraining the harmonics of the oscillating frequency. The VCO was designed according to the proposed structure as well as the conventional structure, and the superiority of the proposed structure was verified through its simulation, fabrication, and measurement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.273-279
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• 2013

In this paper, a novel split ring resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator, and oscillator for 5.8GHz band is designed using proposed split ring resonator. At the fundamental frequency of 5.8GHz, 7.22dBm output power and -83.5 dBc@100kHz phase noise have been measured for oscillator with split ring resonator. The phase noise characteristics of oscillator is improved about 9.7dB compared to one using the general ${\lambda}$/4 microstrip resonator. Because it is possible that varactor diode or lumped capacitor is placed on the gaps of split ring resonator, resonant frequency can be controlled by bias voltage. We can design voltage controlled oscillator using proposed split ring resonator. Thus, due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• Journal of Korea Society of Digital Industry and Information Management
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• v.19 no.2
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• pp.11-25
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• 2023

With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.