• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.511-521
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• 2007

In this paper, we designed and fabricated a Ka-band synthesizer module. In addition, the systematic layout procedure and the test procedure were presented for the construction of compact synthesizer. To implement the Ka-band synthesizer, X-band VCO is employed as VCO and its frequency was multiplied by 3 with frequency tripler. The fabricated frequency synthesizer shows a frequency tuning range of 500 MHz, output power of about 14 dBm, and a phase noise of -96.17 dBc/Hz at the 100 kHz offset frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.139-145
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• 2024

This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K_vco) variation. To compensate conventional large K_vco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K_vco (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.11
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• pp.54-59
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• 2007

In this paper, broadband voltage-controlled oscillator (VCO) using electronically controlled metamaterial transmission line based on varactor-loaded split-ring resonator (VLSRR) is presented. First, it is demonstrated that VLSRR coupled to microstrip line can lead to metamaterial transmission line with tuning capability. The negative effective permeability is provided by the VLSRR in a narrow band above the resonant frequency, which can be bias controlled by virtue of the presence of varactor diodes. The VCO with 1.8 V power supply has phase noise of $-108.84\;{\sim}\;-106.84\;dBc/Hz$ @ 100 Hz in the tuning range, $5.47\;{\sim}\;5.84\;GHz$. The figure of merit (FOM) called power-frequency-tuning-normalized (PFTN) is 20.144 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.85-91
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• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1038-1044
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• 2011

In this paper, the multichannel intermediate frequency transceiver for broadband multimedia system is designed and the experimental results are analyzed. Basic elements of the transceiver such as frequency synthesizer, amplifier, mixer, automatic gain control amplifier are introduced. The analysis technique described here applies not only to amplifier but also to any other nonlinear components such as mixers and frequency doubler. Through the investigation of the power spectrum density of the transmitted signal, the phase noise of the local oscillator is evaluated below 70 dBc/kHz. The frequency characteristics of the modulated signal is flat within the system bandwidth. Also the effects of adjacent channel interference and supurious emission are analyzed. And the function of automatic gain control amplifier is well operated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.784-794
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• 1996

In this papre, the design and the fabrication of the surface mountable voltage controlled oscillator is described for local oscillator in PCS(WACS/TDMA) handset. The VCO employs two silicon bipolar transistors of $f_{gamma}$ of 4 GHz as active devices. These are asembled to form the VCO on the 4 layer PCB of the size $12{\times}10mm$which provides the strip line resonator at the third layer. The fabricated VCO shows tuning rage over 50 MHz, phase noise -100 dBc/Hz at the 100 kHz frequency offset, and 0 dBm output power with the consumption of 22 mA at 3V. It is belived that the size will be more reduced by employing 1005 chip components and that the current consumption will be improved by employing transistors of higher $f_{gamma}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.83-89
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• 2014

A ku-band complementary cross-coupled differential voltage controlled oscillator is designed, measured and fabricated using $0.18-{\mu}m$ CMOS technology. A 2.4GHz of very wide frequency tuning at oscillating frequency of 14.5GHz is achieved with presented circuit topology and MOS varactors. Measurement results show -1.66dBm output power with 18mA DC current drive from 3.3V power supply. When 5V is applied, the output power is increased to 0.84dBm with 47mA DC current. -74.5dBc/Hz phase noise at 100kHz offset is measured. The die area is $1.02mm{\times}0.66mm$.