• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.98-104
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• 2017

This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. Th e measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are $1,080{\mu}m{\times}760{\mu}m$ (PLL1) and $1,100{\mu}m{\times}800{\mu}m$ (PLL2), including the probing pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• Journal of electromagnetic engineering and science
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• v.4 no.3
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• pp.107-112
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• 2004

In this paper, the phase noise of 900 MHz VCO is improved using modified strip line square ring resonator. In order to demonstrate the phase noise improvement of the proposed VCO, the same circuit was manufactured using shorted-circuit resonator. In condition of the same bias current, the phase noise of the proposed VCO with modified square ring resonator is suppressed by 7 dB as - 103 dBc/Hz at 100 kHz offset compared to the conventional VCO with short-circuit resonator. From the proposed VCO, we achieved output power of - 4.8 dBm, harmonics suppression of 16 dB, and tuning bandwidth of 100 MHz. The proposed VCO consumed 5 mA at 3 V, and its size is 1.2 cm ${\times}$ 1.0 cm.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.235-238
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• 2011

In this paper, a novel low phase noise voltage-controlled oscillator (VCO) using metamaterial structure and rat race coupler is presented for reducing the phase noise without the reduction of the frequency tuning range. The metamaterial structure has been realized by microstrip square open loop double split ring resonator (SRR). The rat race coupler shows slightly higher transmission compared to a Wilkinson combiner and is, therefore, used instead to improve the performances of VCO. By providing these unique modifications, the proposed push-push VCO has a phase noise of -126.30~-124.83 dBc/Hz at 100 kHz in the tuning range of 5.672~5.800 GHz.

• Journal of Navigation and Port Research
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• v.27 no.5
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• pp.513-517
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• 2003

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator} applied to X-band as stable source is implementea and constructed with a MESFET for low noise, a dielectric resonator of high frequency selectivity and high Q varactor diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated through the harmonic balance simulation technique to provide the optimum performance. The measured results of a fabricated VCDRO show that output is 2.22dBm at 12.05GHz. harmonic suppression -30dBc. phase noise -130dBc at 100kHz offset. and sweep range of varactor diode $\pm$18.7MHz. respectively. This oscillator will be available to X-band application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.398-402
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• 2003

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator) applied to FMCW(Frequency Modulated Continuous Wave)Radar as stable source is implemented and constructed with a MESFET for low noise, a dielectric resonator of high frequency selectivity, and high Q varator diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated thrash harmonic balance simulation technique to provide the optimum performance. The measured result of a fabricated VCDRO shows that output is 2.22dBm at 12.05GHz, harmonic suppression -30dBc, phase noise -130dBc at 100kHz offset, and sweep range of varator diode $\pm$18.7MHz, respectively. This oscillator will be available to FMCW Radar.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.1
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• pp.7-12
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• 2011

This paper proposes a differential Colpitts-VCO circuit suitable for low phase noise oscillation at the sub-1V supply voltage. Oscillation with low phase noise at the sub-1V supply voltage is facilitated by employing inductors as the current sources of the proposed circuit. One of the two feedback capacitors of the single-ended Colpitts oscillator in the proposed circuit is replaced with the MOS varactor in order to further reduce the resonator loss. Post-layout simulation results using a $0.18{\mu}m$ RF CMOS technology show that the phase noises at the 1MHz offset frequency of the proposed circuit oscillating at the sub-1V supply voltages of 0.6 to 0.9 V are at least 7 dBc/Hz lower than those of the well-known cross-coupled differential VCO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.71-76
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• 2010

In this paper, a 120 GHz local oscillator(LO) for the sub-harmonic mixer in the THz transceiver with a carrier frequency of 240 GHz was designed and fabricated. A 120 GHz local oscillator was composed of 40 GHz PLL(Phase Locked Loop), 40 GHz BPF(Band Pass Filter), frequency tripler and 120 GHz BPF. The commercial model of the frequency tripler was used. The measured result of the 40 GHz PLL showed the phase noise of -105 dBc/Hz at the 100 kHz offset frequency. The measured result of 120 GHz BPF showed the insertion loss of 1.3 dB at center frequency of 119 GHz with bandwidth of 5 GHz. The output power of 120 GHz LO was measured to 6.6 dBm.