• Steel and Composite Structures
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• v.37 no.4
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• pp.447-462
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• 2020

In this paper, a simplified seismic design method for low-rise dual frame-steel plate shear wall (SPSW) structures is proposed in the framework of performance-based seismic design. The dynamic response of a low-rise structure is mainly dominated by the first-mode and the structural system can be simplified to an equivalent single degree-of-freedom (SDOF) oscillator. The dual frame-SPSW structure was decomposed into a frame system and a SPSW system and they were simplified to an equivalent F-SDOF (SDOF for frame) oscillator and an equivalent S-SDOF (SDOF for SPSW) oscillator, respectively. The analytical models of F-SDOF and S-SDOF oscillators were constructed based on the OpenSees platform. The equivalent SDOF oscillator (D-SDOF, dual SDOF) for the frame-SPSW system was developed by combining the F-SDOF and S-SDOF oscillators in parallel. By employing the lateral force resistance coefficients and seismic demands of D-SDOF oscillator, the design approach of SPSW systems was developed. A 7-story frame-SPSW system was adopted to verify the feasibility and demonstrate the design process of the simplified method. The results also show the seismic demands derived by the equivalent dual SDOF oscillator have a good consistence with that by the frame-SPSW structure.

• ETRI Journal
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• v.27 no.1
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• pp.75-80
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• 2005

This paper addresses a fully-integrated low phase noise X-band oscillator fabricated using a carbon-doped InGaP heterojunction bipolar transistor (HBT) GaAs process with a cutoff frequency of 53.2 GHz and maximum oscillation frequency of 70 GHz. The oscillator circuit consists of a negative resistance generating circuit with a base inductor, a resonating emitter circuit with a microstrip line, and a buffering resistive collector circuit with a tuning diode. The oscillator exhibits 4.33 dBm output power and achieves -127.8 dBc/Hz phase noise at 100 kHz away from a 10.39 GHz oscillating frequency, which benchmarks the lowest reported phase noise achieved for a monolithic X-band oscillator. The oscillator draws a 36 mA current from a 6.19 V supply with 47.1 MHz of frequency tuning range using a 4 V change. It occupies a $0.8mm{\times}0.8mm$ die area.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.538-542
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• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.4
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• pp.275-281
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• 2003

A new neural oscillator has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed neural oscillator consists of a nonlinear variable resistor with negative resistance as well as simple transconductors and capacitors. The variable negative resistor which is used as a input stage of the oscillator consists of a positive feedback transconductors and a bump circuit with Gaussian-like I-V curve. The proposed neural oscillator has designed in integrated circuit with SPICE simulations. Simulations of a network of 4 oscillators which are connected with excitatory and inhibitory synapses demonstrate cooperative computation. Measurements of the fabricated oscillator chip with a $\pm$ 2.5 V power supply is shown and compared with the simulated results.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.116-119
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• 2005

In this paper, we propose the PLL system of the local oscillator system for the millimeter wave band's radio astronomy receiving system. The development of the proposed local oscillator system based on the YIG oscillator VCO with 26.5 ${\sim}$ 40GHz specification. This system consists of the oscillator part including the YIG VCO, the harmonic mixer, and the isolator, the RF processing part including the triplexer, limiter, and RF discrimination processor. and the PLL system including YIG modulator and controller. Based on this configuration. we verify the frequency and power stability of the developed local oscillator system according to some temperature variation. From this test results we confirm the stable output frequency and power characteristic performance of the developed La system at constant temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.506-510
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• 2016

A triple-band (TB) oscillator was implemented in the TSMC $0.18{\mu}m$ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt $4^{th}$ order LC resonators to form a $6^{th}$ order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) mA and 2.4(2.29, 2.28) mW, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 GHz, 5.82-6.15 GHz, and 3.68-4.08 GHz. The die area of the triple-band oscillator is $0.835{\times}1.103mm^2$.

• The Journal of the Acoustical Society of Korea
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• v.26 no.2
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• pp.95-101
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• 2007

This paper presents the feasibilityof a thickness mode piezoelectric oscillator to detect damages in structures. The thickness mode oscillator sensor is composed of an electronic feedback oscillator circuit and a piezoelectric thickness mode vibrator to be attached to a structure of interest. Damage to the structure causes a change in the impedance spectrum of the structure, which results in a corresponding change of a resonant frequency of the structure. The oscillator sensor can instantly detect the frequency change in a very simple manner. Feasibility of the piezoelectric oscillator sensor was verified with a sample aluminum plate where artificial cracks of different lengths and number were imposed in sequence. Validity of the measurement was confirmed through comparison of the experimental data with the results of finite element analyses of a plate with cracks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2081-2086
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• 2015

The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.441-446
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• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.682-684
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• 2004

The effect of 1/f noise by the random telegraph signal(RTS) on the phase noise and the jitter of CMOS ring Oscillator is investigated. 10 parallel piece-wise-linear current sources connected to each node model the RTS signals. The In, the power spectral density and the jitter of output of the ring oscillator are simulated as functions of the amplitude and time constant of RTS current source. It is confirmed that the increase of amplitude of RTS is directly related to the increase of the width of phase noise md the value of jitter. The shorter the time constant is, the wider width of FET peak and the larger value of cycle to cycle jitter are.