• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.543-545
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• 2009

With injection-type source delivery system of atomic layer deposition (ALD), bottom-contact and bottom-gate thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric for the first time. The properties of the ZnO TFT were greatly influenced by the device structure and the process conditions. The zinc oxide TFTs exhibited a channel mobility of 0.43 $cm^2$/Vs, a threshold voltage of 0.85 V, a subthreshold slope of 3.30 V/dec, and an on-to-off current ratio of above $10^6$ with solid saturation.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1046-1048
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• 2004

Performances of organic thin film transistors (OTFTs) can be detrimentally affected by the state of the gate dielectric. Because of the bad stability of polymers, OTFTs with polymer gate dielectrics often provide abnormal characteristics. In this study, we report the condensation effect of the polymer gate dielectric layer. For the observations of the effect of the condensation, the spin-coated polymer layers with various deposition conditions were fabricated and left under low vacuum condition for several days. It is observed that the thickness of polymer layer and the electrical characteristic of OTFTs vary with the condensation time.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1103-1106
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• 2006

We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1313-1316
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• 2005

In the present paper, it was investigated that adhesion layer on gate insulator could affect the electrical characteristics for the organic thin film transistors (OTFTs). The polyimide (PI) as organic adhesion layer was fabricated by using the vapor deposition polymerization (VDP) processing . It was found that electrical characteristics improved comparing OTFTs using adhesion layer to another. We researched adhesion layer as a function of thickness. For inverted-staggered top contact structure, field effect mobility, threshold voltage, and on-off current ratio of OTFTs using adhesion layer of PI 15 nm thickness on the gate insulator with a thickness of 0.2 ${\mu}m$ were about 0.5 $cm^2/Vs$, -0.8 V, and $10^6$, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1200-1203
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• 2004

We investigated the molecular aligning capability of a polymer layer containing ceramic nanoparticles which can be used as a gate insulator of organic thin-film transistors (OTFTs). Because of the enhanced dielectric properties arising from the nanoparticles and molecular aligning properties of the polymer, the composite layer provides excellent mobility characteristics of the OTFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1030-1033
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• 2004

We herewith report for the effect of dielectric surface modification on the electrical characteristics of organic thin-film transistors (OTFTs). The kist-jm-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide ($ZrO_2$) gate dielectric layer. The OTFTs are elaborated on the flexible plastic substrates through 4-level mask process to yield a simple fabrication process. In this work, we also have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1348-1351
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• 2007

We demonstrated that the threshold voltage shift owing to a gate-bias stress is originated from the trapped charges at the interface between semiconductor layer and dielectric layer, and such drawback can be settled by applying long-term delay time to the gate electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1115-1118
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• 2006

Using a thermally-crosslinkable organosiloxane-based organic-inorganic hybrid material, solution processable gate dielectric layer for organic thin-film transistors (OTFTs) have been fabricated. The hybrid dielectrics are synthesized by the sol-gel process, followed by the heat-treatment at $190{\bullet}\;.{\bullet}$ To investigate the electrical property of hybrid dielectric, leakage current behavior and capacitance were measured. To fabricate coplanar-type OTFTs, Au/Cr electrode was deposited onto the heavily doped silicon substrate with the organic-inorganic hybrid dielectric layer and then ${\alpha},{\omega}-dihexylquaterthiophene$ was drop-cast between source and drain electrical performance of the fabricated transistor.

• Proceedings of the KIEE Conference
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• 2000.11c
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• pp.455-457
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• 2000

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.