• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.92-97
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• 2000

An AMR(Adaptive Multi-Rate) speech coding algorithm has been adopted as a standard speech codec for IMT-2000. It is based on the algebraic CELP, and consists of eight speech coding modes having the bit rate from 4.75 kbit/s to 12.2 kbit/s. It also contains the VAD(Voice Activity Detector), SCR (Source Controlled Rate) operation, and error concealment scheme for robustness in a radio channel. The bit rate of AMR is changed on a frame basis depending on the channel condition. In this paper, we introduced AMR speech coding algorithm and performed the real-time implementation using TMS320C6201, i.e., a Texas Instrument's fixed-point DSP. With the ANSI C source code released from ETSI and 3GPP, we convert and optimize the program to make it run in real time using the C compiler and assembly language. It is verified that the decoded result of the implemented speech codec on the DSP is identical with the PC simulation result using ANSI C code for test sequences. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.311-314
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• 2000

Multicasting is the delivery of a packet simultaneously to one or more destinations using a single, local transmit operation. Typically the set of destinations is referred to as a multicast group. sources transmit to these group addresses without knowing the group's actual membership. We have studied an implementation of one model of supporting IP multicast over ATM, the Multicast over ATM model developed by the IETF(Internet Engineering Task Force). MCOA(Multicast over ATM) that includes both these modes of operation and the behavior of each in a testbed where the ATM host were connected in a WAN and LAN. WAN topology was to gain insight into the effects of larger propagation delays on the MC over ATM model.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.113-115
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• 2008

At the high speed operation, the high demagnetization voltage can reduce the negative torque, so the output power and efficiency can be improved. In this paper, a novel power converter for single phase SRM with high demagnetization voltage is proposed. A simple passive capacitor circuit is added in the front-end, which consists of three diodes and one capacitor. Based on this passive network, the two capacitors can be connected in series and parallel, so the phase winding of SRM obtains general do-link voltage in excitation mode and the double dc-link voltage in demagnetization mode. The operation modes of the proposed converter are analyzed in detail. Some computer simulation results is done to verify the performance of proposed converter.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.8
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.273-276
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• 2005

Performance analysis of a solid oxide fuel cell/micro gas turbine hybrid system is conducted at design-point and part-load conditions and its results are discussed in this study. With detailed considerations of the heat and mass transfer phenomena along various flow streams of the SOFC, the analysis based on a quasi-2D model reasonably predicts its performance at the design-point operating conditions. In case of part-load operations, performance of the hybrid system to three different operation modes(fuel only control, speed control, and VIGV control) is compared. It is found that the simultaneous control of both supplied fuel and air to the system with a variable MGT rotational speed mode is the optimum choice for the high performance operation. And then, the dynamic characteristics of a solid oxide fuel cell are briefly introduced.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Journal of Power Electronics
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• v.9 no.5
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• pp.809-821
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• 2009

This paper proposes a new phase-shift full-bridge DC-DC converter by applying energy recovery circuits to a conventional full-bridge DC-DC converter in plasma display panel applications. The converter can achieve soft-switching in main-switches by an extra auxiliary resonant network even with the wide operating condition of both output load and input voltage. The un-coupled design guidelines to the main bridge-leg component parameters for soft-switching operation contribute to conduction loss reduction in the transformer primary side leading to efficiency improvement. The auxiliary switches in the resonant network also operate in zero-current switching. This paper analyzes the operation modes of the proposed scheme and presents the key design guidelines through steady state analysis. Also, the paper verifies the validity of the circuits by hardware experiments with a 1kW DC/DC converter prototype.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.05a
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• pp.340-343
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• 2007

In this paper, we present our method to reduce vibration of the base plate of a refrigerator by avoiding resonance between base plate and compressor operation. To verify the modes of the base plate, FE models of the base plate with free-free condition and applied boundary condition were built and validated by results from experimental modal analysis. Operating Deflection Shape analysis was applied to find the sensitive area on the base plate during compressor operation. In optimization process, Finite Difference Method - based sensitivity analysis is used to detect the most sensitive area. Finally, based on this numerical result, we will make beads on the base plate to reduce vibration of refrigerator.

• Journal of the Korean Operations Research and Management Science Society
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• v.23 no.4
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• pp.33-51
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• 1998

The industrial operation is one of the three basic modes of shipping operation with liner and Tramp operations. Industrial operators usually control vessels of their own or on a time charter to minimize the cost of shipping their cargoes. Such operations abound in shipping of bulk commodities, such as oil, chemicals and ores. This work is concerned with an operational optimization analysis of the fleet owned by a major oil company. a typical industrial operator. The operational optimization problem of the fleet of a major oil company is divided Into two phase problem. The front end corresponds to the optimization problem of the transportation of crude oil. product mix. and the distribution of product oil to comply with the demand of the market. The back end tackles the scheduling optimization problem of the fleet to meet the seaborne transportation demand derived from the front end. A case study reflecting the practices of an international major oil company is demonstrated to make clear the underlying ideas.