• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.260-266
• /
• 2013

The open bit line is vulnerable to noise compared to the folded bit line when read/write for the DRAM. According to the increasing DRAM densities, the core circuit operating conditions is exacerbated by the noise when it comes to the open bit line 6F2(F : Feature Size) structure. In this paper, the interference effects were analyzed by the data patterns between the bit line by experiments. It was beyond the scope of existing research. 68nm Tech. 1Gb DDR2, Advan Tester used in the experiments. The noise effects appears the degrade of internal operation margin of DRAM. This paper investigates sense amplifier power line splits by experiments. The noise can be improved by 0.2ns(1.3%)~1.9ns(12.7%), when the sense amplifier power lines split. It was simulated by 68nm Technology 1Gb DDR2 modeling.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.11a
• /
• pp.3-5
• /
• 2000

1.8V,4Gb DDR SDRAM설계 및 제작을 수행하였다. DRAM동작 시 발생하는 Bit Line간 CouplingNoise를 보상하기 위한 Twisted Open Bit Line 구조를 제안하였다. Low Voltage Operation으로 인한 Bit Line Sense Amplifier 의 동작 저하를 보상하기 위한 BL S/A Pre-Sensing 방식 및 Reference Bit Line Voltage Calibration 구조를 제안하였다. Chip면적 증가로 인한 동작속도 감소의 보상을 위해 Repeater Driver 구조를 Core 및 Periphery Circuit에 적용하여 동작 대비 Chip 면적의 증가를 최소화 하도록 하였다.

• ETRI Journal
• /
• v.26 no.6
• /
• pp.583-588
• /
• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.7B
• /
• pp.695-705
• /
• 2002

In this paper, we propose a simple open loop transmit diversity (TD) scheme for the wideband code division multiple access (W-CDMA) systems in Rician multipath fading channels such as rural area or satellite channels where line-of-sight (LOS) paths are in presence. The proposed scheme does not require any pre-processing of transmit data, resulting in simpler structure as compared to conventional closed loop transmit adaptive array (TxAA) and open loop space-time transmit diversity (STTD). We analytically derive the probability density function of signal-to-noise ratio at the Rake receiver output and the uncoded bit error rate performance of the proposed scheme. Extensive simulation is Performed to verify the analytical performance of the proposed scheme under typical Rician multipath fading channel environments. Moreover, comparative results with the conventional TxAA and STTD are also provided. Simulation results show that the proposed scheme shows slightly better performance than the conventional open loop STTD under the channels with very weak LOS components, however, it significantly outperforms the STTD under the channels with dominant LOS components, and achieves a close performance of ideal closed loop TxAA.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.839-842
• /
• 1998

The wide spread of multimedia system demands a large viewin gdesply device which can inform a message to many peoples in open area. This paper is about the design, simulating and testing of a large viewing LED pannel control ASIC(application specific integrated circuit). This LED pannel control ASIC runs on 16 bit microprocessor MC68EC000 and has following functions:16 line interlaced LED pannel controller, memory controller, 16 channel priority inerrupt controller, 2 channel direct memory access controller, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16byte FIFO, IBM PC/AT compatible keyboard interface, battery backuped real time clock, ISA bus controller, battery backuped 256 byte SRAM and watech dog timer. The 0.6micron CMOS sea of gate is used to design the ASIC in amount of about 39,000 gates.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.5
• /
• pp.1351-1361
• /
• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.

• ETRI Journal
• /
• v.35 no.1
• /
• pp.1-6
• /
• 2013

In this paper, we present an implemented serial 40-Gb/s receiver optical subassembly (ROSA) module by employing a proposed TO-CAN package and flexible printed circuit board (FPCB). The TO-CAN package employs an L-shaped metal support to provide a straight line signal path between the TO-CAN package and the FPCB. In addition, the FPCB incorporates a signal line with an open stub to alleviate signal distortion owing to an impedance mismatch generated from the soldering pad attached to the main circuit board. The receiver sensitivity of the ROSA module measures below -9 dBm for 40 Gb/s at an extinction ratio of 7 dB and a bit error rate of $10^{-12}$.

• Journal of the Korean Professional Engineers Association
• /
• v.16 no.3
• /
• pp.5-23
• /
• 1983

On the Seoul Metropolitan Subway Construction of No. 3, 4 Line, the total length is 57 Km and it is now undergoing almost 55％ progress. The working method is classified into Open Cut of 70% and the rest of 30% tunnelling method in the 48 job site. Above tunnelling method is execute by American Steel Support System and the rest of 10 job site carried out by New Austria Tunnelling Method. This paper describes Blasting Standardizations works on the above Tunnelling ' Open Cut Method under big slogan, first safety, second execution. As a superintendent, I strived standardization of works with Better powder, Better Drills ' Better Pattern. Geological structure of Seoul area is composed by Jurassic Granite and also the above rockgroup are over burden by Alluviums as a Unconformity. First of all, I carried out the standard amount of powder and burden through experimental standard blasting by each powder as following Blasting works in the subway construction is surrounding shop Building, under pass the city river and also under pass highest building basement floor. I made allowable Blasting Vibration Value by West-Germany Vornorm DIN 4150, Teil 3 and should measure each blasting works as fellows all of powder is used basically Low-Gravity and Low Velocity such as Slurry, Ammonium Nitrate ' Finex I, II. for Smooth Blasting Instead of Gelatin Dynamite. Electric Detonation Cap is used basically M/S Delay Cup instead of Electric delay ' Simultaneous cap. I applied following formula V=KW3/4 $D^{-2}$ V=Particle Velocity (Cm/sec) K=Ginh Huh's Value W=Delay Charge (Kg) D=Distance(m) In the Open Cut, within 1m distance from H-pile I made to use the Concrete breaker, as following V=7W/$^{0.5}$V/$^{-1.75}$ On the Concentrate Building area, I advise to use Light class drill ø36m Bit and advance 1.1m per round blasting the three boom jumbo drill over ø45mm used only suburb of city.e Light class drill ø36m Bit and advance 1.1m per round blasting the three boom jumbo drill over ø45mm used only suburb of city.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.7
• /
• pp.657-666
• /
• 2002

In this paper, a new broadband phase shifter to adjust the slope of dispersive phase characteristic for frequency of transmission network was proposed. The new fundamental network consists of a fixed main line with a length of λ/2 at the center frequency and two double stubs, each with a length of λ/8 at the center frequency, which are open and shorted, respectively, and which are shunted at the edge points of the main line. Characteristic impedances of the main line and two parallel double stubs are adjusted to produce a minimum phase error and to obtain an input and output match at the desired phase shift. Especially, the proposed structure is especially suitable for a broadband phase shifter with large phase shifts more than 90$^{\circ}$, and it is operated in the octave bandwidth. To verify the usefulness of a new broadband phase shifter, each 45$^{\circ}$-, 90$^{\circ}$-, 180$^{\circ}$-bit phase shifter and 3-bit phase shifter(45$^{\circ}$-phase step), which is cascaded in series, operated at the center frequency 3 GHz were designed, fabricated and experimented. The measured results were in very close agreement with the corresponding simulation results over the bandwidth of I/O impedance match and phase error for each phase shift.

• International journal of advanced smart convergence
• /
• v.13 no.3
• /
• pp.48-58
• /
• 2024

Fiber to the Home (FTTH) technology is among the most advanced broadband services, delivering voice, data, and television through a single optical fiber directly to customer premises, ensuring high-speed and reliable connectivity. The study conducted on Nepal Telecom's FTTH networks involved direct measurements from the optical line terminal to the fiber access point and optical network unit, providing detailed insights into network performance. Using the OptiSystem software, the analysis revealed a link loss of 24.99 dB, a Q-factor of 12.98, and a minimum Bit Error Rate (BER) of 7.31E-39, all within standard limits, which underscores the robustness of the network. The study also identified that the highest contributors to signal loss were connector loss, fiber attenuation, and fusion splices, emphasizing the importance of minimizing these factors to maintain optimal network performance. Overall, these findings highlight the critical aspects of FTTH network design and maintenance, ensuring that service providers can deliver high-quality broadband services to customers.