• Journal of Chest Surgery
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• 제50권3호
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• pp.153-162
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• 2017

Background: The mesenchymal-epithelial transition factor (MET) receptor can be overexpressed in solid tumors, including small cell lung cancer (SCLC). However, the molecular mechanism regulating MET stability and turnover in SCLC remains undefined. One potential mechanism of MET regulation involves the C-terminus of Hsp70-interacting protein (CHIP), which targets heat shock protein 90-interacting proteins for ubiquitination and proteasomal degradation. In the present study, we investigated the functional effects of CHIP expression on MET regulation and the control of SCLC cell apoptosis and invasion. Methods: To evaluate the expression of CHIP and c-Met, which is a protein that in humans is encoded by the MET gene (the MET proto-oncogene), we examined the expression pattern of c-Met and CHIP in SCLC cell lines by western blotting. To investigate whether CHIP overexpression reduced cell proliferation and invasive activity in SCLC cell lines, we transfected cells with CHIP and performed a cell viability assay and cellular apoptosis assays. Results: We found an inverse relationship between the expression of CHIP and MET in SCLC cell lines (n=5). CHIP destabilized the endogenous MET receptor in SCLC cell lines, indicating an essential role for CHIP in the regulation of MET degradation. In addition, CHIP inhibited MET-dependent pathways, and invasion, cell growth, and apoptosis were reduced by CHIP overexpression in SCLC cell lines. Conclusion: C HIP is capable of regulating SCLC cell apoptosis and invasion by inhibiting MET-mediated cytoskeletal and cell survival pathways in NCI-H69 cells. CHIP suppresses MET-dependent signaling, and regulates MET-mediated SCLC motility.

• Journal of electromagnetic engineering and science
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• 제11권4호
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• KSBB Journal
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• 제25권4호
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• pp.344-350
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• 2010

This paper demonstrates a microfluidic chip incorporating patterned hollow silica beads that can be effectively used for chemotaxis assay. The hollow silica bead has been exploited to develop a carrier for chemoattractant to induce cell migration. The microfluidic chip contains a patterned array of microfabricated docks which can hold only one bead per docking site. The hollow bead placed inside microfluidic chip releases chemotactic reagent (PDGF-BB) around its periphery in a controlled fashion which generates a signal for chemotatic migration of fibroblast cells. The number of cells migrated close to each bead has been assessed. On-chip cell migration assay showed a remarkable result proving the high efficiency and reliable accuracy in quantitative analysis. Therefore, the device could be extensively used in cell migration assay and other various studies related to cellular movements.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.985-988
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• 1997

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study ,a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented in up end milling process using measured cutting forces. Size effect was identified from the analysis of specific cutting resistance obtained by using the modified undeformed chip section area.

• 한국전기전자재료학회논문지
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• 제18권6호
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• pp.506-509
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• 2005

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2000년도 추계학술대회논문집 - 한국공작기계학회
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• pp.279-284
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• 2000

The object of this paper is to evaluate the chip breakability using the experimental equation of surface roughness, which is developed in turning by an orthogonal array method. L$\sub$9/(3$^4$) orthogonal array method, one of fractional factorial design has been used to study effects of main cutting parameters such as cutting speed, feed rate and depth of cut, on the surface roughness. The evaluation of chip breakability is used the chip breaking index(C$\sub$B/), non-dimensional parameter. And the analysis of variance (ANOYA)-test has been used to check the significance of cutting parameters. Using the result of ANOYA-test, the experimental equation of chip breakability, which consists of significant cutting parameters, has been developed. The coefficient of determination of this equation is 0.866.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• 전기전자학회논문지
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• 제16권4호
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• pp.405-409
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• 2012

In this paper, on-chip antennas applicable to ultra low power wireless transceiver are designed and evaluated. Using $0.18{\mu}m$ SiGe MMIC process, 4 types of antenna with $1{\times}1mm^2$ dimensions are fabricated. The on-wafer measurement in a microwave probe station is conducted to measure the input VSWR and antenna performance of the designed on-chip antenna. Performance evaluation results show that developed antennas can be easily integrated into one-chip RF transceiver for ubiquitous applications, including WPAN and human body communications.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.103-106
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• 2005

This paper reports design and fabrication of CMOS temperature sensor circuit using MOSIS 0.25um CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. This circuit may be applicable to the design of one-chip IC where quartz crystal resonator is directly mounted on CMOS oscillator chips.