• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.739-741
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• 1993

This paper deals with the Improvement of inverter output waveform with space vector modulation using the DSP-chip. The proposed scheme can be considered as a alternative of the conventional, subharmonic method. This scheme features a maximum output voltage that is 15% greater. The number of switchings is also 30% less than the one obtained by subharmonic modulation method(SHM) A performance function(PF) which is the time integral function of the inverter output voltage is introduced in this paper. An optimal PWM pattern is obtained by minimizing the distortion factor of performance function. The experiment was carried out with an TMS320C25.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.596-599
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• 2003

In this paper, we designed the digital pulse motor control chip including a circular interpolation function. The proposed algorithm in this paper is a nonparametric cure generation algorithm (Jordan's algorith) and a very simple algorithm. So the design for this algorithm used a small number of gates. Also an average error is fairly low. The max output speed is 4Mpps(Pulse per second), the max input frequency is 16MHz and the chip is useful for the stepping and servo motors. The software contains one or two, and many axes linear interpolation algorithm and two axes circular interpolation algorithm.

• Journal of the Korean Society for Precision Engineering
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• v.7 no.2
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• pp.47-57
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• 1990

In-process recognition of the cutting states is one of the very important technologies to increase the reliability of mordern machining process. In this study, practical methods which use the dynamic component of the cutting force are proposed to recognize cutting states (i.e. chip formation, tool wear, surface roughness) in turning process. The signal processing method developed in this study is efficient to measure the maximum amplitude of the dynamic component of cutting force which is closely related to the chip breaking (cut-off frequency : 80-500 Hz) and the approximately natural frequency of cutting tool (5, 000-8, 000 Hz). It can be clarified that the monitoring of the maximum apmlitude in the dynamic component of the cutting force enables the state of chip formation which chips can be easily hancled and the inferiority state of the machined surface to be recognized. The microcomputer in-process tool wear monitor- ing system introduced in this paper can detect the determination of the time to change cutting tool.

• International journal of advanced smart convergence
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• v.11 no.2
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2022.11a
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• pp.247-248
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• 2022

The microfluidic controlled droplet production system is one of the most powerful methods for capsule manufacturing. However, stable production is not possible when the powder is included. We solved the above problem by developing an off-chip droplet production system. we checked the droplet creation mechanism and created a simple repair model. It was possible to produce a uniform and stable droplet regardless of the powder content.

• Journal of Internet Computing and Services
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• v.25 no.3
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• pp.1-8
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• 2024

As the Internet of Things (IoT) has gained significant prominence in our daily lives, most IoT devices rely on over-the-air technology to automatically update firmware or software remotely via the network connection to relieve the burden of manual updates by users. And preserving security for OTA interface is one of the main requirements to defend against potential threats. This paper presents a simulation of an attack scenario on the commoditized System-on-a-chip, ESP32 chip, utilized for drones during their OTA update process. We demonstrate three types of attacks, WiFi cracking, ARP spoofing, and TCP SYN flooding techniques and postpone the OTA update procedure on an ESP32 Drone. As in this scenario, unpatched IoT devices can be vulnerable to a variety of potential threats. Additionally, we review the chip to obtain traces of attacks from a forensics perspective and acquire memory forensic artifacts to indicate the SYN flooding attack.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1546-1555
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• 2001

Conventionally, in a CDMA system analysis, we assume only a single path within one chip duration. But, in this paper, we assume various number of multipaths within one chip duration according to spreading bandwidth in fixed channel model. Thus we take into account of the effects of autocorrelation and relative phases among multipath components within one chip duration according to different bandwidth, and analyze fading effects. And we derive the pdf of output signal. Then, we derive the average error probability versus the number of users from derived pdf. We use a Maximal Ratio Combining (MRC) RAKE receiver under the JTC channel model which is one of the popular realistic wideband channel models. And we employ hybrid FDMA/CDMA systems to compare the performance of W-CBMA system for the same occupied total bandwidth. Then, we compare and analyze them for different bandwidth based on the number of users as a parameter. From the simulation results for different bandwidth, better performance can be obtained for wider bandwidth system where more resolvable multipath components are available.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Asian Pacific Journal of Cancer Prevention
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• v.14 no.3
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• pp.1687-1689
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• 2013

We performed a case-control study to investigate whether SNPs of CHIP might affect the development of IA in Chinese Han nationality. We believe we are the first to have screened IA patients for mutations in the CHIP gene to determine the association with these variants. The study group comprised 224 Chinese Han nationality patients with at least one intracranial aneurysm and 238 unrelated healthy Han nationality controls. Genomic DNA was isolated from blood leukocytes. The entire coding regions of CHIP were genotyped by PCR amplification and DNA sequencing. Differences in genotype and allele frequencies between patients and controls were tested by the chi-square method. Genotype and allele frequencies of the SNP rs116166850 was demonstrated to be in Hardy-Weinberg equilibrium. No significant difference in genotype or allele frequencies between case and control groups was detected at the SNP. Our data do not support the hypothesis of a major role for the CHIP gene in IA development in the Chinese Han population.