• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.79-80
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• 2007

A high performance organic phototransistor with dynamic range of 120 dB is demonstrated by employing soluble pentacene as a photo-sensing layer. The organic phototransistor used suspended source/drain (SSD) electrode structure, which provides a dark current level of ${\sim}10^{-14}$ A at positive gate bias. Under a steady-state illumination, the organic phototransistor exhibited a current modulation of $10^6$ compared to dark to give a dynamic range of 120 dB. These results suggest that the organic phototransistor based on TIPS pentacene can be a new premising candidate for low-cost and high-performance photo-sensing element for digital imaging applications.

• Korean Chemical Engineering Research
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• v.48 no.4
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• pp.511-514
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• 2010

Perfluorinated polymer($Cytop^{TM}$) was deposited on selective area of AlGaN/GaN HEMT structure using low cost and simple spin-coating method, and the electrical characteristics of the device was analyzed for application of passivation layer on semiconductors. Gate lag measurement results of $Cytop^{TM}$ passivated and unpassivated HEMT were compared. Passivated device shows improved 65 % pulsed drain current of dc mode value. Rf measurements were also performed. $Cytop^{TM}$ passivated HEMT have similar rf performance to PECVD grown $Si_3N_4$ passivated device. $Cytop^{TM}$ passivation layer may play an important role in mitigating surface state trapping in the region between gate and drain.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.63-66
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• 1998

Prototype MFSFET′s using ferroelectric oxide LiNbO$_3$ as a gate insulator have been successfully fabricated with the help of 2 sheets of metal masks and demonstrated nonvolatile memory operations of the MFSFET′s. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were 600 $\textrm{cm}^2$/V.s and 0.16 mS/mm, respectively. The drain current of the "on" state was more than 4 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 0.5 V, which means the memory operation of the MFSFET. A write voltage as low as $\pm$3 V, which is applicable to low power integrate circuits, was used for polarization reversal.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2324-2332
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• 2017

This paper presents the electrical performances of novel AlGaSb/InGaAs heterojunction-based vertical-tunneling field-effect transistor (VTFET). The device performance was investigated in views of the on-state current ($I_{on}$), drain-induced barrier thinning (DIBT), and subthreshold swing (SS) as the gate length ($L_G$) was scaled down. The proposed TFET with a $L_G$ of 5 nm operated with an $I_{on}$ of $1.3mA/{\mu}m$, a DIBT of 40 mV/V, and an SS of 23 mV/dec at a drain voltage ($V_{DS}$) of 0.23 V. The proposed TFET provided approximately 25 times lower DIBT and 12 times smaller SS compared with the conventional $L_G$ of 5 nm TFET. The AlGaSb/InGaAs VTFET showed extremely high scalability and strong immunity against short-channel effects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.32-38
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• 2003

This works reports the measurement and analysis results on the hot electron induced device degradation in Gate-All-Around SOI MOSFET's, which were fabricated using commercially available SIMOX material. It is observed that the worst-case condition of the device degradation in nMOSFETs is $V_{GS}$ = $V_{TH}$ due to the higher impact ionization rate when the parasitic bipolar transistor action is activated. It is confirmed that the device degradation is caused by the interface state generation from the extracted degradation rate and the dynamic transconductance measurement. The drain current degradation with the stress gate voltages shows that the device degradation of pMOSFETs is dominantly governed by the trapping of hot electrons, which are generated in drain avalanche hot carrier phenomena.r phenomena.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.25-28
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• 1999

Metal ferroelectric semiconductor Field Effect- Transistors(MFSFET) with various gate electrodes, that are aluminum, platinum and poly -Si, using LiNbO$_3$/Si(100) structures were fabricated and the properties of the FETs have been discussed. The drain current of the state of FET with Pt electrode was more than 3 orders of magnitude larger than the state current at the same gate voltage of 1.5 V, 7.rich means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about 10$^3$s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.78-81
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• 2015

Pure ZnO and ZnO nanowires doped with 3 wt.% Ga (‘3GZO’) were grown by pulsed laser deposition in a furnace system. The doping of Ga in ZnO nanowires was analyzed by observing the optical and chemical properties of the doped nanowires. The diameter and length of nanowires were under 200 nm and several ${\mu}m$, respectively. Changes of significant resistance were observed and the sensitivities of ZnO and 3GZO nanowires were compared. The sensitivities of ZnO and 3GZO nanowire sensors measured at 300℃ for 1 ppm of ethanol gas were 97% and 48%, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• ETRI Journal
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• v.24 no.4
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• pp.328-331
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• 2002

We investigated the electrical characteristics of p-channel double-diffused MOSFETs (p-LDMOSFETs) with an uneven racetrack source (URS) and a conventional racetrack source (CRS) for PDP driver IC applications. The breakdown voltage of the p-LDMOSFET with the URS in offstate was nearly the same as the p-LDMOSFET with the CRS. However, the breakdown voltage of the p-LDMOSFET with the URS in on-state was about 30% higher than that of the p-LDMOSFET with the CRS, while the saturated drain current of the p-LDMOSFET with the URS was only about 4% lower than that of the p-LDMOSFET with the CRS.