• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.41 no.5
• /
• pp.283-290
• /
• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• Korean Journal of Mathematics
• /
• v.28 no.4
• /
• pp.791-802
• /
• 2020

We obtain a two variable generating function for the number of triangular partitions. Using this generating function, we study arithmetic properties of a certain weighted count of triangular partitions. Finally, we introduce a rank-type function for triangular partitions, which gives a combinatorial explanation for a triangular partition congruence.

• Journal of the Korea Concrete Institute
• /
• v.17 no.6 s.90
• /
• pp.1045-1051
• /
• 2005

For critical structures and application, where a given reliability must be met, it is necessary to account for uncertainties and variability in material properties, structural parameters affecting the corrosion process, in addition to the statistical and decision uncertainties. This paper presents an approach to the fuzzy arithmetic based modeling of the chloride-induced corrosion of reinforcement in concrete structures that takes into account the uncertainties in the physical models of chloride penetration into concrete and corrosion of steel reinforcement, as well as the uncertainties in the governing parameters, including concrete diffusivity, concrete cover depth, surface chloride concentration and critical chloride level for corrosion initiation. The parameters of the models are regarded as fuzzy numbers with proper membership function adapted to statistical data of the governing parameters and the fuzziness of the corrosion time is determined by the fuzzy arithmetic of interval arithmetic and extension principle

• Journal of Korea Multimedia Society
• /
• v.11 no.6
• /
• pp.816-827
• /
• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.3B
• /
• pp.584-591
• /
• 2000

In distributed arithmetic-based architecture for an inner product between two length-N vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA( distributed arithmetic ) is proposed. The proposed method is based on modified OBC( offset binary coding) and control circuit reduction technique. by simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50%.

• Journal of the Korea Computer Graphics Society
• /
• v.6 no.3
• /
• pp.1-7
• /
• 2000

The number of pixels being processed in a raster graphics system often exceeds 1 million per frame. Replacing fractional arithmetic by integer arithmetic on rendering graphics primitives will therefore significantly improve the rendering performance. A scaling method that replaces fractional arithmetic by integer arithmetic on rendering graphics primitives is introduced. This method is applied to the filtered edge drawing and Gouraud shading. This method will also be applicable to some of other incremental algorithms for rendering graphics primitives. Because the scaling method requires only simple modifications upon the known algorithms that already have been implemented in ASIC (Application Specific Integrated Circuit), our algorithms can easily be implemented in ASIC. Our method will be useful especially for the low-price systems (e.g., home game machines, personal computers, etc.).

• Journal of Applied and Pure Mathematics
• /
• v.6 no.3_4
• /
• pp.105-117
• /
• 2024

In the classical sense, it is known that it is impossible to construct a vector space over the entire set of real numbers with the help of simple interval arithmetic. In this article, it has shown that a vector space can be constructed in the classical sense by helping Markov's extended interval arithmetic on the interval valued Cesaro sequence spaces of non-absolute type. As a result of the positive answers, this idea was extended by us with some theorems. Consequently, a new perspective was gained to the construction of new types of sequence spaces by using different algebraic operations on interval-valued sequence spaces.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.9
• /
• pp.11-20
• /
• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Communications of the Korean Mathematical Society
• /
• v.38 no.2
• /
• pp.355-364
• /
• 2023

In this paper, we investigate the sums of the elements in the finite set $\{x^k:1{\leq}x{\leq}{\frac{n}{m}},\;gcd_u(x,n)=1\}$, where k, m and n are positive integers and gcd_u(x, n) is the unitary greatest common divisor of x and n. Moreover, for some cases of k and m, we can give the explicit formulae for the sums involving some well-known arithmetic functions.

• School Mathematics
• /
• v.11 no.4
• /
• pp.567-581
• /
• 2009

Many articles have reported that zero causes children's arithmetic errors. This article was designed to measure the effect of zero on children's arithmetic performances. For this, 222 of 3,4,5,6 graders in elementary school were tested with pencil and paper. The test were categorized into four parts: basic number fact, column subtraction, column multiplication, and column division. These data showed that the negative effect of zero on children's arithmetic was limited to several areas, concretely, multiplication facts with zero, column subtraction with numbers which have two successive zeros, column multiplication with numbers which have zero in a middle position, long division with zeros. But there was no evidence that students could self-control these negative effects of zero as grade went up. It implies that we should keep attention to children's arithmetic performance with zero in some special areas.