• Title/Summary/Keyword: ns-2 simulation

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Electro-Thermal Characteristics of Hole-type Phase Change Memory (Hole 구조 상변화 메모리의 전기 및 열 특성)

  • Choi, Hong-Kyw;Jang, Nak-Won;Kim, Hong-Seung;Lee, Seong-Hwan;Yi, Dong-Young
    • Journal of Advanced Marine Engineering and Technology
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    • v.33 no.1
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    • pp.131-137
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    • 2009
  • In this paper, we have manufactured hole type PRAM unit cell using phase change material $Ge_2Sb_2Te_5$. The phase change material $Ge_2Sb_2Te_5$ was deposited on hole of 500 nm size using sputtering method. Reset current of PRAM unit cell was confirmed by measuring R-V characteristic curve. Reset current of manufactured hole type PRAM unit cell is 15 mA, 100 ns. And electro and thermal characteristics of hole type PRAM unit cell were analyzed by 3-D finite element analysis. From simulation temperature of PRAM unit cell was $705^{\circ}C$.

VLSI Design and Implementation of Inversion and Division over GF($2^m$) for Elliptic Curve Cryptographic System (타원 곡선 암호 프로세서용 GF($2^m$) Inversion, Division 회로 설계 및 구현)

  • 현주대;최병윤
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1027-1030
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    • 2003
  • In this paper, we designed GF(2$^{m}$ ) inversion and division processor for Elliptic Curve Cryptographic system. The processor that has 191 by m value designed using Modified Euclid Algorithm. The processor is designed using 0.35 ${\mu}{\textrm}{m}$ CMOS technology and consists of about 14,000 gates and consumes 370 mW. From timing simulation results, it is verified that the processor can operate under 367 Mhz clock frequency due to 2.72 ns critical path delay. Therefore, the designed processor can be applied to Elliptic Curve Cryptographic system.

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2-bit Flash ADC Based on Current Mode Algorithmic

  • Tipsuwanporn, V.;Chuenarom, S.;Maitreechit, S.;Chuchotsakunleot, W.;Kongrat, V.
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.473-473
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    • 2000
  • This paper presents the 2-bit parallel algorithmic ADC using current mode for parallel method algorithm. It is operated by parallel conversion, 2-bit at each moment, and increase bit numbers by serial connection. The circuit operates in current mode. The comparison ratio can be controlled while working under mode operation. The circuit design used 0.8 ${\mu}{\textrm}{m}$ CMOS technology which capable to convert 2-bit in 50 ns, power consumed 0.786 nW, with input current 0-50 mA from 3V single supply. From simulation testing, the conversion rate is much faster than other method.

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Active Routing Mechanism for Mobile IP Network (모바일 IP 네트워크를 위한 액티브 라우팅 매커니즘)

  • Soo-Hyun Park;Hani Jang;Lee-Sub Lee;Doo-Kwon Baik
    • Journal of the Korea Society for Simulation
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    • v.12 no.3
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    • pp.55-68
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    • 2003
  • As mobile IP has been suggested only to support mobility of mobile station(MS) by which it dose nothing but guarantee MS's new connection to the network, it is for nothing in Quality of Service(QoS) after handoff of MS. QoS is very important factor in mobile IP network to provide multimedia applications and real-time services in mobile environment, and it is closely related to handoff delay Therefore as a main issue in mobile IP research area, handoff delay problem is actively studied to guarantee and promote QoS. In this paper, in order to resolve such a problem, we suggest Simple Network Management Network(SNMP) information-based routing that adds keyword management method to information-based routing in active network, and then propose QoS controlled handoff by SNMP information-based routing. After setting up routing convergence time, modeling of suggested method and existing handoff method is followed in order to evaluate the simulations that are carried out with NS-2. The result of simulation show the improvement of handoff delay, and consequently it turns off the QoS has been improved considerably.

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SECURITY FRAMEWORK FOR VANET: SURVEY AND EVALUATION

  • Felemban, Emad;Albogamind, Salem M.;Naseer, Atif;Sinky, Hassan H.
    • International Journal of Computer Science & Network Security
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    • v.21 no.8
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    • pp.55-64
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    • 2021
  • In the last few years, the massive development in wireless networks, high internet speeds and improvement in car manufacturing has shifted research focus to Vehicular Ad-HOC Networks (VANETs). Consequently, many related frameworks are explored, and it is found that security is the primary issue for VANETs. Despite that, a small number of research studies have taken into consideration the identification of performance standards and parameters. In this paper, VANET security frameworks are explored, studied and analysed which resulted in the identification of a list of performance evaluation parameters. These parameters are defined and categorized based on the nature of parameter (security or general context). These parameters are identified to be used by future researchers to evaluate their proposed VANET security frameworks. The implementation paradigms of security frameworks are also identified, which revealed that almost all research studies used simulation for implementation and testing. The simulators used in the simulation processes are also analysed. The results of this study showed that most of the surveyed studies used NS-2 simulator with a percentage of 54.4%. The type of scenario (urban, highway, rural) is also evaluated and it is found that 50% studies used highway urban scenario in simulation.

Dynamic Power Management For Energy Efficient Wi-Fi Direct (에너지 효율적인 Wi-Fi Direct를 위한 동적 전력 관리 기법)

  • Seo, Youn;Ko, Young-Bae
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38B no.8
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    • pp.663-671
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    • 2013
  • Recently, the Wi-Fi Direct standard based on WLAN is getting more attention as a new technology for enabling D2D(Devide-to-Device) communications on mobile devices. However, due to limited power resource of mobile devices and, an energy inefficiency problem can be an issue. In order to solve this problem, the Wi-Fi Direct defines two power management schemes: Opportunistic scheme and Notice of Absence(NoA) scheme. However, there is no concrete description of which power management scheme would be better for when. In this paper, via comprehensive simulation studies using ns-3, we show that each scheme presents obviously different performance and energy efficiency according to data traffic patterns. We then propose more energy efficient way of dynamically switching the two power management schemes.

Enhanced Peer-to-Peer Streaming Protocol to Provide The Selective VoD Service in Live Streaming Session (스트리밍 세션에서 선택적 VoD 서비스 제공을 위한 향상된 피어-투-피어 스트리밍 프로토콜)

  • Yi, Seonwoo;Cho, Sunghyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.1
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    • pp.40-47
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    • 2015
  • We propose a method to provide a selective VoD service during live streaming sessions. In the proposed method, each peer joined the live streaming session receives video stream packets with P2P manner and stores the packets to provide a VoD service. To mitigate the overhead of each peer node to store the video stream packets, the proposed scheme categorizes peers into three different groups based on their link types. To increase data gathering speed and reduce the network load, we also proposes the P2P transmission scheme within the same AP network for the peers with Wi-Fi link. To evaluate the performance of the proposed method, we implement computer simulator using NS-3. Simulation results show that the proposed method reduces the overhead about 66% and increases the P2P data gathering speed about 50% compared to the conventional schemes.

A Delay Tolerant Vehicular Routing Protocol for Low Vehicle Densities in VANETs (차량 밀도가 낮은 VANET 환경을 위한 지연 허용 차량 라우팅 프로토콜)

  • Cha, Si-Ho;Ryu, Min-Woo;Cho, Kuk-Hyun
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.49 no.4
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    • pp.82-88
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    • 2012
  • A VANET (Vehicular Ad Hoc Network), a subclass of MANET (Mobile Ad Hoc Network), is an ad hoc network using wireless communication between vehicles without fixed infrastructure such as base station. VANET suffers a frequent link breakage and network topology change because of the rapid movement of vehicles and the density change of vehicles. From these characteristics of VANET, geographical routing protocols such as GPSR (Greedy Perimeter Stateless Routing) using only the information of neighbor nodes are more suitable rather than AODV and DSR that are used in existing MANETs. However, GPSR may have a transmission delay and packet loss by frequent link disconnection and continual local maxima under the low vehicle density conditions. Therefore, in this paper, we propose a DTVR (Delay Tolerant Vehicular Routing) algorithm that perform a DTN-based routing scheme if there is no 2-hop neighbor nodes for efficient routing under the low vehicle densities in VANETs. Simulation results using ns-2 reveal that the proposed DTVR protocol performs much better performance than the existing routing protocols.

Design of BCH Code Decoder using Parallel CRC Generation (병렬 CRC 생성 방식을 활용한 BCH 코드 복호기 설계)

  • Kal, Hong-Ju;Moon, Hyun-Chan;Lee, Won-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.13 no.2
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    • pp.333-340
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    • 2018
  • This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

High-speed Design of 8-bit Architecture of AES Encryption (AES 암호 알고리즘을 위한 고속 8-비트 구조 설계)

  • Lee, Je-Hoon;Lim, Duk-Gyu
    • Convergence Security Journal
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    • v.17 no.2
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    • pp.15-22
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    • 2017
  • This paper presents new 8-bit implementation of AES. Most typical 8-bit AES designs are to reduce the circuit area by sacrificing its throughput. The presented AES architecture employs two separated S-box to perform round operation and key generation in parallel. From the simulation results of the proposed AES-128, the maximum critical path delay is 13.0ns. It can be operated in 77MHz and the throughput is 15.2 Mbps. Consequently, the throughput of the proposed AES has 1.54 times higher throughput than the other counterpart although the area increasement is limited in 1.17 times. The proposed AES design enables very low-area design without sacrificing its performance. Thereby, it can be suitable for the various IoT applications that need high speed communication.