• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.6
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• pp.9-14
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• 2011

We have investigated the electrical properties of $AlO_x$ thin film device. The device has been fabricated top-bottom electrode structure and its transport properties are measured in order to study the resistance change. Electrical properties with linear voltage sweep on a electrodes are used to show the variation of resistance of $AlO_x$ thin film device. Fabricated $AlO_x$ thin film device with MIM structure is changed from a high conductive On-state to a low conductive Off-state by the external linear voltage sweep. It is found that the initial resistance of the $AlO_x$ thin film is low-resistance On state and reversible switching occurs. Consequently, we believe $AlO_x$ thin film is a promising material for a next-generation nonvolatile memory and other electrical applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of Information Technology Services
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• v.12 no.4
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• pp.369-380
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• 2013

The advent of the state-of-the-art technologies such as cloud computing and big data processing stimulates the provision of various new IT services, which implies that more servers are required to support them. However, the need for more servers will lead to more energy consumption and the efficient use of energy in the computing environment will become more important. The next generation nonvolatile RAM has many desirable features such as byte addressability, low access latency, high density and low energy consumption. There are many approaches to adopt them especially in the area of the file system involving storage devices, but their focus lies on the improvement of system performance, not on energy reduction. This paper suggests a novel approach for energy reduction in which the MRAM-based SSD is utilized as a storage device instead of the hard disk and a downsized page is adopted instead of the 4KB page that is the size of a page in the ordinary file system. The simulation results show that energy efficiency of a new approach is very effective in case of accessing the small number of bytes and is improved up to 128 times better than that of NAND Flash memory.

• Journal of the Korean institute of surface engineering
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• v.55 no.5
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• pp.247-260
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• 2022

Since the first report on ferroelectricity in Si-doped hafnia (HfO2), this emerging ferroelectrics have been considered promising for the next-generation semiconductor devices with their characteristic nonvolatile data storage. The robust ferroelectricity in the sub-10-nm thickness regime has been proven by numerous research groups. However, extending their scalability below the 5 nm thickness with low temperature processes compatible with the back-end-of-line technology. In this review, therefore, the current status, technical issues, and their potential solutions of atomic layer deposition (ALD) of HfO₂-based ferroelectrics are comprehensively reviewed. Several technical issues in the physical scaling of the ferroelectric thin films and potential solutions including advanced ALD techniques including discrete feeding ALD, atomic layer etching, and area selective ALD are introduced.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.408-408
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• 2012

It is well known that magnetic random access memory (MRAM) is nonvolatile memory devices using ferromagnetic materials. MRAM has the merits such as fast access time, unlimited read/write endurance and nonvolatility. Although DRAM has many advantages containing high storage density, fast access time and low power consumption, it becomes volatile when the power is turned off. Owing to the attractive advantages of MRAM, MRAM is being spotlighted as an alternative device in the future. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal- oxide semiconductor (CMOS). MTJ stacks are composed of various magnetic materials. FePt thin films are used as a pinned layer of MTJ stack. Up to date, an inductively coupled plasma reactive ion etching (ICPRIE) method of MTJ stacks showed better results in terms of etch rate and etch profile than any other methods such as ion milling, chemical assisted ion etching (CAIE), reactive ion etching (RIE). In order to improve etch profiles without redepositon, a better etching process of MTJ stack needs to be developed by using different etch gases and etch parameters. In this research, influences of $O_2$ gas on the etching characteristics of FePt thin films were investigated. FePt thin films were etched using ICPRIE in $CH_4/O_2/Ar$ gas mix. The etch rate and the etch selectivity were investigated in various $O_2$ concentrations. The etch profiles were studied in varying etch parameters such as coil rf power, dc-bias voltage, and gas pressure. TiN was employed as a hard mask. For observation etch profiles, field emission scanning electron microscopy (FESEM) was used.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.272-272
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• 2011

무기물 나노입자를 포함하는 유기물/무기물 나노복합체는 차세대 전자 소자에 쉽게 적용이 가능하고 응용 잠재적 능력이 뛰어나기 때문에 차세대 비휘발성 메모리 소자에 응용하려는 연구가 세계적으로 활발히 진행되고 있다. 본 연구에서는 poly (methylmethacrylate) (PMMA) 절연성 고분자 박막 안에 CdTe와 CdTe-CdSe 코어-쉘 나노입자를 각각 분산시켜 이를 전하의 저장 매체로 사용하는 메모리 소자를 제작하였다. 제작된 각각의 소자에 대한 메모리 메카니즘과 PMMA 박막 안에 분포되어 있는 CdTe-CdSe 코어-쉘 나노입자에서 CdSe 쉘의 전기적 영향에 대하여 연구하였다. 소자에 필요한 용액을 제작하기 위해 서로 다른 용매에 녹아 있는 CdTe-CdSe 나노입자와 PMMA를 혼합하였다. Al 금속을 하부 전극으로 증착한 p-Si (100) 기판 위에 나노입자와 PMMA가 혼합된 용액을 스핀 코팅 방법을 사용하여 박막을 형성한 후, 남아있는 용매를 제거하기 위해 열처리를 하였다. 용매가 모두 제거된 박막위에 금속 마스크를 사용하여 상부 Al 전극을 열증착 방법으로 형성하였다. 나노입자가 포함된 고분자 박막의 메모리 특성을 비교하기 위하여 나노입자가 없는 PMMA층만으로 형성된 소자도 같은 방법으로 제작하였다. 세 가지 종류의 소자에 고주파 정전용량-전압 (C-V) 측정을 한 결과 나노입자가 분산된 PMMA 층으로 제작된 소자에서만 평탄 전압 이동이 관찰되었으며, 이것은 나노입자를 전하 포획 장소로 사용할 수 있다는 것을 확인하였다. 정전용량-시간 (C-t) 측정을 하여 나노입자가 포함된 PMMA 층으로 제작된 메모리 소자의 안정성을 관찰하였다. C-V와 C-t 측정 자료를 바탕으로 제작된 메모리 소자의 메모리 메카니즘과 CdTe-CdSe 코어-쉘 나노입자에서 CdSe 쉘의 역할을 설명하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.156-157
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• 2012

단일 셀에서 비휘발성 및 고속의 휘발성 메모리를 모두 구동할 수 있는 다기능 메모리는 모바일 기기 및 embedded 장치의 폭발적인 성장에 있어 그 중요성이 커지고 있다. 따라서 최근 이러한 fusion기술을 응용한 unified RAM (URAM)과 같은 다기능 메모리의 연구가 주목 받고 있다. 이러한 다목적 메모리는 주로 silicon on insulator (SOI)기반의 1T-DRAM과 SONOS기술 기반의 비휘발성 메모리의 조합으로 이루어진다. 하지만 이런 다기능 메모리는 주로 단결정기반의 SOI wafer 위에서 구현되기 때문에 값이 비싸고 사용범위도 제한되어 있다. 따라서 이러한 다기능메모리를 다결정 실리콘을 이용하여 제작한다면 기판에 자유롭게 메모리 적용이 가능하고 추후 3차원 적층형 소자의 구현도 가능하기 때문에 다결정실리콘 기반의 메모리 구현은 필수적이라고 할 수 있겠다. 본 연구에서는 다결정실리콘을 이용한 channel recessed구조의 다기능메모리를 제작하였으며 각 1T-DRAM 및 NVM동작에 따른 memory 특성을 살펴보았다. 실험에 사용된 기판은 상부 비정질실리콘 100 nm, 매몰산화층 200 nm의 SOI구조의 기판을 이용하였으며 고상결정화 방법을 이용하여 $600^{\circ}C$ 24시간 열처리를 통해 결정화 시켰다. N+ poly Si을 이용하여 source/drain을 제작하였으며 RIE시스템을 이용하여 recessed channel을 형성하였다. 상부 ONO게이트 절연막은 rf sputter를 이용하여 각각 5/10/5 nm 증착하였다. $950^{\circ}C$ N2/O2 분위기에서 30초간 급속열처리를 진행하여 source/drain을 활성화 하였다. 계면상태 개선을 위해 $450^{\circ}C$ 2% H2/N2 분위기에서 30분간 열처리를 진행하였다. 제작된 Poly Si MFM에서 2.3V, 350mV/dec의 문턱전압과 subthreshold swing을 확인할 수 있었다. Nonvolatile memory mode는 FN tunneling, high-speed 1T-DRAM mode에서는 impact ionization을 이용하여 쓰기/소거 작업을 실시하였다. NVM 모드의 경우 약 2V의 memory window를 확보할 수 있었으며 $85^{\circ}C$에서의 retention 측정시에도 10년 후 약 0.9V의 memory window를 확보할 수 있었다. 1T-DRAM 모드의 경우에는 약 $30{\mu}s$의 retention과 $5{\mu}A$의 sensing margin을 확보할 수 있었다. 차후 engineered tunnel barrier기술이나 엑시머레이저를 이용한 결정화 방법을 적용한다면 device의 특성향상을 기대할 수 있을 것이다. 본 논문에서는 다결정실리콘을 이용한 다기능메모리를 제작 및 메모리 특성을 평가하였다. 제작된 소자의 단일 셀 내에서 NVM동작과 1T-DRAM동작이 모두 가능한 것을 확인할 수 있었다. 다결정실리콘의 특성상 단결정 SOI기반의 다기능 메모리에 비해 낮은 특성을 보여주었으나 이는 결정화방법, high-k절연막 적용 및 engineered tunnel barrier를 적용함으로써 해결 가능하다고 생각된다. 또한 sputter를 이용하여 저온증착된 O/N/O layer에서의 P/E특성을 확인함으로써 glass위에서의 MFM구현의 가능성도 확인할 수 있었으며, 차후 system on panel (SOP)적용도 가능할 것이라고 생각된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.469-472
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• 1999

CeO$_2$ thin films have used in wide applications such as SOI, buffer layer, antirflection coating, and gate dielectric layer. CeO$_2$takes one of the cubic system of fluorite structure and shows similar lattice constant (a=0.541nm) to silicon (a=0.543nm). We investigated CeO$_2$films as buffer layer material for nonvolatile memory device application of a single transistor. Aiming at the single transistor FRAM device with a gate region configuration of PZT/CeO$_2$ /P-Si , this paper focused on CeO$_2$-Si interface properties. CeO$_2$ films were grown on P-type Si(100) substrates by 13.56MHz RF magnetron sputtering system using a 2 inch Ce metal target. To characterize the CeO$_2$ films, we employed an XRD, AFM, C-V, and I-V for structural, surface morphological, and electrical property investigations, respectively. This paper demonstrates the best lattice mismatch as low as 0.2 % and average surface roughness down to 6.8 $\AA$. MIS structure of CeO$_2$ shows that breakdown electric field of 1.2 MV/cm, dielectric constant around 13.6 at growth temperature of 200 $^{\circ}C$, and interface state densities as low as 1.84$\times$10$^{11}$ cm $^{-1}$ eV$^{-1}$ . We probes the material properties of CeO$_2$ films for a buffer layer of FRAM applications.

• Journal of Ceramic Processing Research
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• v.20 no.5
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• pp.484-489
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• 2019

VO2 is an attractive candidate as a transition metal oxide switching material as a selection device for reduction of sneak-path current. We demonstrate deposition of nanoscale VO2 thin films via thermal atomic layer deposition (ALD) with H2O reactant. Using this method, we demonstrate VO2 thin films with high-quality characteristics, including crystallinity, reproducibility using X-ray diffraction, and X-ray photoelectron spectroscopy measurement. We also present a method that can increase uniformity and thin film quality by splitting the pulse cycle into two using scanning electron microscope measurement. We demonstrate an ON / OFF ratio of about 40, which is caused by metal insulator transition (MIT) of VO2 thin film. ALD-deposited VO2 films with high film uniformity can be applied to next-generation nonvolatile memory devices with high density due to their metal-insulator transition characteristic with high current density, fast switching speed, and high ON / OFF ratio.

• Journal of the Korean Ceramic Society
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• v.34 no.2
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• pp.202-208
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• 1997

Bi-layered SrBi2Ta2O9(SBT) films were deposited on Pt/Ti/SiO2/Si sibstrates by rf magnetron sputt-ering at room temperature and then were annealed at 75$0^{\circ}C$, 80$0^{\circ}C$ and 85$0^{\circ}C$ for 1 hour in oxygen at-mosphere. The film composition of SrBi2Ta2O9 was obtained after depositing at room temperature and annealing at 80$0^{\circ}C$. Excess 20mole% Bi2O3 and 30 mole% SrCO3 were added to the target to compensate for the lack of Bi and Sr in SBT film. 200 nm thick SBT film exhibited and dense microstructure, adielectric constant of 210, and a dissipation factor of 0.05 at 1 MHz frequency. The films exhibited Curie temperature of 32$0^{\circ}C$ and a dielectric constant of 314 at that temperature under 100 kHz frequency. The remanent polarization(2Pr) and the coercive field(2Ec) of the SBT films were 9.1 $\mu$C/$\textrm{cm}^2$ and 85 kV/cm at an applied voltage of 3V, resspectively and the SBT film showed a fatigue-free characteristics up to 1010 cy-cles under 5V bipolar pulse. The leakage current density of the SBT film was about 7$\times$10-7A/$\textrm{cm}^2$ at 150 kV/cm. Fatigue-free SBT films prepared by rf magnetron sputtering can be suitable for application to non-volatile memory device.