• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.170-172
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• 2002

The epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristic and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35 V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with the persistent electron trapping, which shows the potential use for a room temperature application.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.33-36
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• 1994

The characteristics of the nonvolatile MONOS memory devices as the nitride thickness is scaled down while maintaining constant tunneling oxide thickness and blocking oxide thickness have been investigated in order to obtain the 5V-programmable E$^2$PROM. We have found that 1V memory window for a 5V programming voltage and 10 year data retention can be achieved in the scaled MONOS memory devices with a 50 blocking oxide, a 57 nitride and a 19 tunneling oxide.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.395-396
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• 2008

There is difficulty in predicting the program efficiency of NOR type nonvolatile memory device adopting channel hot electron injection (CHEI) as program operation mechanism accurately since MOSFET on SOI has floating body. In this study, the dependence of program efficiency for SOI nonvolatile memory device of 200 nm channel length on SOI depletion conditions, partial depletion and full depletion, was quantitatively investigated with the aid of numerical device simulation [1].

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.918-922
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• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.15-16
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a new material of PRAM with $Ge_1Se_1Te_2$. This material has been propose to solve the high energy consumption and high programming current. We have investigated the phase transition behaviors in function of various process factor including contact size, cell size, and annealing time. As a result, we have observed that programming voltage and writing current of $Ge_1Se_1Te_2$ are more improved than $Ge_2Sb_2Te_5$ material.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.14-17
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• 1992

To analyze Nonvolatile SNOSFET(polySilicon-Nitride-Oxide-Semiconductor Field Effect Transistor) memory device, two dimensional numerical computer simulation program was developed. The equation discretization was performed by the Finite difference method and the solution was derived by the Iteration method. The doping profile of n-channel device which was fabricated by 1Mbit CMOS process was observed. The electrical potential and the carrier concentration distribution to applied bias condition were observed in the inner of a device. As a result of the write and the erase to memory charge quantity, the threshold voltage shift is expected. Therefore, without device fabrication, the operating characteristics of the device was observed under various the processing and the operating condition.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.189-190
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• 2008

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated. The band structure of stacked tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with that of the conventional tunneling barrier. The band-gap engineered tunneling barriers show the lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.