• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.159-162
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• 2002

Ferroelectric $YMnO_{3}$ thin films were etched with $Ar/Cl_{2}$ and $CF_{4}/Cl_{2}$ inductivly coupled plasma (ICP). The maximum etch rate of $YMnO_{3}$ thin film was $300{\AA}/min$ at a $Ar/Cl_{2}$ gas mixing ratio of 2/8, a RF power of 800 W, a dc bias of 200 V, a chamber pressure of 15 mTorr, and a substrate temperature of ${30^{\circ}C}$. From the X-ray photoelectron spectroscopy (XPS) analysis ， yttrium not only etched by chemical reactions with Cl radicals, but also assisted by Ar ion bombardments in $Ar/Cl_{2}$ plasma. In $CF_{4}/Cl_{2}$ plasma, yttrium are remained on the etched surface of $YMnO_{3}$ and formed of nonvolatile YFx compounds Manganese etched effectively by chemical reactions with Cl and F radicals. From the X-ray diffraction (XRD) analysis, the (0004) diffraction peak intensity of the $YMnO_{3}$ thin film etched in $Ar/Cl_{2}$ plasma shows lower value than that in $CF_{4}/Cl_{2}$ plasma. It is indicates that the crystallinty of $YMnO_{3}$ thin film is more easily damaged by the Ar ion bombardment than the changes of stoichiometry due to nonvolatile etch by-products.

• 한국식품영양과학회지
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• 제7권2호
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• pp.25-28
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• 1978

한국(韓國) 재래식(在來式) 간장중(中) 불휘발성(不揮發性) amines를 정제확인(精製確認) 및 정량(定量)하여 다음과 같은 결과(結果)를 얻었다. 1. 불휘발성(不揮發性) amine으로 tyramine, histamine을 검출(檢出)했다. 2. Sakaguchi reagent에 양성(陽性)인 미지(未知) spot 2개(個)를 확인(確認)했다. 3. 염농도(鹽濃度) 28.5% 간장의 숙성중(熟性中) tyramine함량(含量)은 거의 변화(變化)가 없었다. 4. 염농도(鹽濃度) 22.0% 간장에서 tyramine 및 histamine, 염농도(鹽濃度) 28.5% 간장에서 histamine은 숙성(熟成)과 더불어 증가(增加)하고 특(特)히 숙성(熟成) 80일(日)에 급격히 증가(增加)하는 경향이었다. 5. 한국(韓國) 재래식(在來式) 간장중(中) tyramine 및 histamine의 함량(含量)은 일본(日本) 간장중(中)에서 보다 훨씬 그 양(量)이 적었다.

• 전자공학회논문지D
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• 제35D권3호
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• pp.39-45
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• 1998

SrBi$_{2}$Ta$_{2}$O$_{9}$ (SBT) ferroelectric thin films for nonvolatile memory were prepared on Pt/Ti/SiO$_{2}$/Si and RuO$_{2}$/SiO$_{2}$/Si substrates by RF magnetron sputtering. The dependences of crystalline and electrical properties on the lower electrode type(Pt and RuO$_{2}$) and the annealing temperatures were investigated. SBT films regardless of their electrode types showed typeical Bi layered peroviskite crystal structures. The crystalline quality of as-deposited SBT films was improved by the rapid thermal annealing at 650.deg. C for 30 sec. The remanetn polarization of 2Pr (Pr+-Pr-) of the annealed SBT films deposited on Pt/Ti/SiO$_{2}$/Si substrates were about 11 .mu.C/cm$^{2}$ and 3 .mu.C/cm$^{2}$, respectively. The leakage currents at 3 V bias voltage were about 0.8 .mu.A/cm$^{2}$ for SBT/ Pt/Ti/SiO$_{2}$/Si and about 1 .mu.A/cm$^{2}$ for SBT/RuO$_{2}$/SiO$_{2}$/Si sample. SBT films annealed at 650 .deg. C showed no degradation in Pr values after 10$^{11}$ polarization switching cycles, indicating good fatigue properties. In addition, for SBT samples deposited on Pt/Ti/SiO$_{2}$/Si, Pr values increased to more than that of initial state, suggesting the increament of leakage current caused by repeated polarization.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• 한국컴퓨터정보학회논문지
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• 제26권11호
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• pp.11-19
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• 2021

본 논문은 충전식 배터리의 단점을 보완하여 급속 충전과 방전이 가능하고 높은 전력 효율 및 반영구적인 충·방전 사이클 수명의 특성을 갖는 수퍼커패시터를 보조 전력 저장장치로 사용하여 전력 관리 시스템에 결합한 프로토타입 플랫폼을 제안한다. 본 논문의 플랫폼을 위해 물리적인 환경 변화에 따른 태양광 패널에서의 공급 전력 차단 혹은 재개 상태를 마이크로컨트롤러에 연결된 인터럽트를 통해 감지할 수 있는 기법을 개발하였다. 연속적인 전원 공급이 보장되지 않는 컴퓨팅 환경에서 데이터의 유실을 방지하기 위해 전원 공급이 차단되는 경우 휘발성 메모리에 있는 프로그램 문맥 및 데이터를 비휘발성 메모리로 이전하는 낮은 수준의 시스템 소프트웨어를 마이크로컨트롤러에 구현하였다. 실험을 통해 슈퍼커패시터가 보조 전력 저장장치로서 일시적 전원 공급에 효과적으로 하는지를 검증하였으며 다양한 벤치마크를 통해 전원 상태 감지 및 휘발성 메모리에서 비휘발성 메모리로의 프로그램 문맥 및 데이터의 이전 기법이 낮은 오버헤드를 갖음을 확인하였다.

• 한국진공학회지
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• 제18권4호
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• pp.302-309
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• 2009

쇼트키 장벽 관통 트랜지스터에 실리콘 나노점을 부유 게이트로 사용하는 비휘발성 메모리 소자를 제작하였다. 소스/드레인 영역에 어븀 실리사이드를 형성하여 쇼트키 장벽을 생성하였으며, 디지털 가스 주입의 저압 화학 기상 증착법으로 실리콘 나노점을 형성하여 부유 게이트로 이용하였다. 쇼트키 장벽 관통 트랜지스터의 동작 상태를 확인하였으며, 게이트 전압의 크기 및 걸어준 시간에 따른 트랜지스터의 문턱전압의 이동을 관찰함으로써 비휘발성 메모리 특성을 측정하였다. 초기 ${\pm}20\;V$의 쓰기/지우기 동작에 따른 메모리 창의 크기는 ${\sim}5\;V$ 이었으며, 나노점에 충분한 전하 충전을 위한 동작 시간은 10/50 msec 이었다. 그러나 메모리 창의 크기는 일정 시간이 지난 후에 0.4 V로 감소하였다. 이러한 메모리 창의 감소 원인을 어븀 확산에 따른 결과로 설명하였다. 본 메모리 소자는 비교적 안정한 쓰기/지우기 내구성을 보여주었으나, 지속적인 쓰기/지우기 동작에 따라 수 V의 문턱전압 이동과 메모리 창의 감소를 보여주었다. 본 실험 결과를 가지고 실리콘 나노점 부유게이트가 쇼트키 장벽 트랜지스터 구조에 접목 가능하여 초미세 비휘발성 메모리 소자로 개발 가능함을 확인하였다.

• 한국결정성장학회지
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• 제14권4호
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• pp.151-154
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• 2004

Issues of ferroelectric high-density memories (>64 Mb) indispensable for upcoming ubiquitous era have been on the cell integration less than $0.1\;\mu\textrm{m}^2$ and reliabilities. Thus nanoscale control of microstructures of ferroelectric films with large switching polarization has been one of the issues to obtain the uniform electrical properties for realization of high-density memories. In this study the grain orientations and distributions of BT-based films by spin-on coatings were examined by FEG-SEM/EBSD. Ferroelectric domain characteristics by PFM were also performed to study the dependence of reliabilities on the grain orientations and distributions. It is believed that understandings of the nucleation and growth mechanisms of the a- or b-axis oriented films during the thermal processes such as RTA and furnace annealing affecting on grain orientation and uniformity could be possible based on our experimental results.

• 한국세라믹학회지
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• 제46권3호
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• pp.336-343
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• 2009

Nickel oxide thin films exhibit the resistive switching as a function of applied voltages. The switching phenomena involve low and high resistance states after electroforming. The electrical features are believed to be associated with the formation and rupture of filaments. The set and reset behaviors are controlled by the oxidation and reduction of filaments. The indirect evidence of filaments is corroborated by the presence of nanocrystalline nickel oxides found in high-resolution transmission electron microscopy. The insertion of insulating layers seems to control the current-voltage characteristics by preventing the continuous formation of conductive filaments, potentially leading to artificial control of resistive behaviors in NiO-based systems.