• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.282-284
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• 2010

1962년 Gallager에 의해서 처음 제안된 LDPC 부호는 터보부호(turbo codes)와 마찬가지로 Shannon의 채널용량 한계(channel capacity limit)에 가까운 성능을 보였지만 당시 기술력으로 구현이 불가능한 복잡도로 인해 오랫동안 잊혀져왔다. 1995년 Mackay 와 Neal은 이를 재발견하였고 간단한 확률적 복호법을 이용하여 LDPC 부호의 성능이 매우 우수함을 보였다. 또한 1997년 Mackay는 q>2일 때 LDPC 부호를 GF(q)상에서 구성할 경우에 성능이 더 좋아짐을 보였다. 본 논문에서는 이진 bit로 구성된 같은 길이의 정보 비트(information bit)를 통해 16-QAM 변조를 사용했을시 Binary LDPC 부호와 Non Binary LDPC 부호의 성능을 비교 분석하고, 최적의 성능을 가지는 LDPC 부호의 설계에 대해 제안한다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• Journal of Communications and Networks
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• v.12 no.5
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• pp.406-410
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• 2010

This paper presents an approach to the construction of non-binary quasi-cyclic (QC) low-density parity-check (LDPC) codes based on multiplicative groups over one Galois field GF(q) and Euclidean geometries over another Galois field GF($2^S$). Codes of this class are shown to be regular with girth $6{\leq}g{\leq}18$ and have low densities. Finally, simulation results show that the proposed codes perform very wel with the iterative decoding.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.328-338
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• 2015

Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: Spatially coupled low-density parity-check (LDPC) codes, nonbinary LDPC codes, and polar coding.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1954-1971
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• 2017

In this work, first, a multiuser detection (MUD) algorithm based on component-level soft interference cancellation and linear minimum mean square error (CLSIC-LMMSE) is proposed, which can enhance the bit error ratio (BER) performance of the traditional SIC-LMMSE-based MUD by mitigating error propagation. Second, for non-binary low density parity check (NB-LDPC) coded high-order modulation systems, when the proposed algorithm is integrated with partial mapping, the receiver with iterative detection and decoding (IDD) achieves not only better BER performance but also significantly computational complexity reduction over the traditional SIC-LMMSE-based IDD scheme. Extrinsic information transfer chart (EXIT) analysis and numerical simulations are both used to support the conclusions.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.339-345
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• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.3
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• pp.127-139
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• 2014

In this paper, we present two signal processing techniques for designing binary error correction codes for Multi-Level Cell(MLC) NAND flash memory. MLC NAND flash memory saves the non-binary symbol at each cell and shows asymmetric channel LLR l-density which makes it difficult to design soft-decision binary error correction codes such as LDPC codes and Polar codes. Therefore, we apply density mirroring and EM algorithm for approximating the MLC NAND flash memory channel to the binary-input memoryless channel. The density mirroring processes channel LLRs to satisfy roughly all-zero codeword assumption, and then EM algorithm is applied to l-density after density mirroring for approximating it to mixture of symmetric Gaussian densities. These two signal processing techniques make it possible to use conventional code design algorithms, such as density evolution and EXIT chart, for MLC NAND flash memory channel.