1 |
H. G. Lee, S.-R. Kim, M.-K Lee, J.-J. Kong and D.-J. Shin, "The threshold voltage control method for mitigating cell-to-cell interference in multi-level cell NAND flash memory," in Proc. KICS Int. Conf. Commun. 2012(KICS ICC 2012), pp. 79-80, Seoul, South Korea, Nov. 2012.
|
2 |
D. Park and J. Lee, "Performance of the coupling canceller with the various window size on the multi-level cell NAND flash memory channel," J. KICS, vol. 37A, no. 8, pp. 706-711, Aug. 2013.
과학기술학회마을
DOI
ScienceOn
|
3 |
D. Lee and W. Sung, "Adaptive quantization scheme for multi-level cell NAND flash memory," J. KICS, vol. 38C, no. 6, pp. 540-549, Jun. 2013.
과학기술학회마을
DOI
ScienceOn
|
4 |
S.-Y. Chung, T. J. Richardson, and R. L. Urbanke, "Analysis of sum product decoding of low-density parity-check codes using a Gaussian approximation," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 657-679, Feb. 2001.
DOI
ScienceOn
|
5 |
S.-Y. Chung, G. D. Forney, T. J. Richardson, and R. L. Urbanke, "On the design of low-density parity-check codes within 0.0045 dB of the shannon limit," IEEE Commun. Lett., vol. 5, pp. 58-60, Feb. 2001.
DOI
ScienceOn
|
6 |
T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.
DOI
ScienceOn
|
7 |
J. Hou, P. H. Siegel, L. B. Milstein, and H. D. Pfister, "Capacity-approaching bandwidthefficient coded modulation schemes based on low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 49, no. 9, pp. 2141-2155, Sep. 2003.
DOI
ScienceOn
|
8 |
G. Dong, N. Xie, and T. Zhang, "On the use of soft-decision error-correction codes in NAND flash memory," IEEE Trans. Circuits and Syst., vol. 58, no. 2, pp. 429-439, Feb. 2011.
DOI
ScienceOn
|
9 |
G. Dong, S. Li, and T. Zhang, "Using data post-compensation and pre-distortion to tolerate cell-to-cell interference in MLC NAND flash memory," IEEE Trans. Circuits and Syst., vol. 57, no. 10, pp. 2718-2728, Oct. 2010.
DOI
ScienceOn
|
10 |
H. Choi, W. Liu, and W. Sung, "VLSI implementation of BCH error correction for multilevel cell NAND flash memory," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 843-847, May 2010.
DOI
ScienceOn
|
11 |
T. J. Richardson and R. L. Urbanke, "The capacity of low-density parity-check codes under message passing decoding," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 599-618, Feb. 2001.
DOI
ScienceOn
|
12 |
E. Arikan, "Channel polarization : A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels," IEEE Trans. Inf. Theory, vol. 55, no. 7, pp. 3051-3073, Jul. 2009.
DOI
ScienceOn
|
13 |
S. ten Brink, "Convergence behavior of iteratively decoded parallel concatenated codes," IEEE Trans. Commun., vol. 49, pp. 1727-1737, Oct. 2001.
DOI
ScienceOn
|
14 |
R. Mori and T. Tanaka, "Performance and construction of polar codes on symmetric binary-input memoryless channels," in Proc. IEEE Symp. Inf. Theory, pp. 1496-1500, Seoul, South Korea, Jun. 2009.
|
15 |
C. Yang, Y. Emre, and C. Chakrabatri, "Product code schemes for error correction in MLC NAND flash memories," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. vol. 29, no. 12, pp. 2302-2314, Dec. 2012.
|
16 |
C.-C. Wang, S. R. Kulkarni, and H. V. Poor, "Density evolution for asymmetric memoryless channels," IEEE Trans. Inf. Theory, vol. 51, no. 12, pp. 4216-4236, Dec. 2005.
DOI
ScienceOn
|
17 |
C. M. Bishop, Pattern Recognition and Machine Learning, Cambridge, UK: Springer, 2006.
|
18 |
B. Lu, G. Yue, and X. Wang, "Performance analysis and design optimization of LDPC-coded MIMO OFDM systems," IEEE Trans. Signal Processing, vol. 52, no. 2, pp. 348-361, Feb. 2004.
DOI
ScienceOn
|