• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.583-591
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• 2008

OFDM (orthogonal frequency division multiplexing) has serious problem of high PAPR (peak-to-average power ratio). Recently, CI/OFDM (carrier interferometry OFDM) system has been proposed for the low PAPR. However, CI/OFDM system shows another problem of ICI because of phase offset mismatch due to the phase noise. In this paper, to simultaneously reduce the PAPR and ICI effects, we propose an A-CI/OFDM (advanced-CT/OFDM). This method improves the BER performance by use of the margin of phase offset at CI codes. Propose system to reduce the effect the phase noise, even though it shows a little bit higher PAPR than conventional CI/OFDM, so we apply the PTS among the PAPR reduction techniques to proposed system to mitigate this problem. Therefore, it improves the total BER performance because the proposed method can decrease the effect of phase noise and get the gain in PAPR reduction performance. From the simulation results, we can show the performance comparison between the conventional OFDM, CI/OFDM and A-CI/OFDM.

• Journal of Satellite, Information and Communications
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• v.1 no.1
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• pp.54-58
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• 2006

A new design for easily controlling operating frequency of an antenna-integrated planar oscillator is introduced. The oscillator circuit of a broadband negative-resistance active part and a passive load including a patch antenna. The patch resonance is used for determining the oscillation frequency. This design reduces the possibility of mismatch between antenna radiation and oscillation frequencies. To achieve optimum output power, load-pull simulation for the negative-resistance circuit is used. The load-pull simulation shows the feed point and the delay of feed line can affect the oscillation power. Two negative-resistance circuits capable of supporting oscillation over full C-band and X-band are fabricated. The oscillation frequency, output power and phase noise for different patch antennas are measured.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.292-299
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• 2015

An envelope elimination and restoration transmitter that uses a tri-level envelope encoding scheme is presented for improving the efficiency and linearity of the system. The proposed structure amplifies the same magnitude signal regardless of the input peak-to-average power ratio and reduces the quantization noise by spreading out the noise to the out-of-band frequency, resulting in the enhancement of power efficiency. An improved linearity is also obtained by providing a new timing mismatch calibration technique between the envelope and phase signal. Implementation in a 130 nm CMOS process, transmitter measurements on a 20-MHz long-term evolution input signal show an error vector magnitude of 3.7 % and an adjacent channel leakage ratio of 37.5 dBc at 2.13 GHz carrier frequency.

• Journal of Broadcast Engineering
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• v.18 no.3
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• pp.455-462
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• 2013

This paper introduces the Spatially Preprocessed Speech Distortion Weighted Multi-channel Wiener Filter (SP-SDW-MWF) for multi-microphone noise reduction and proposes a method to determine the speech distortion weights. The SP-SDW-MWF is known as a robust noise reduction algorithm against the error caused by the mismatch in microphones. The SP-SDW-MWF adopts weights which determine the amount of noise reduction at the expense of introducing speech distortion in the noise-suppressed speech. In this paper, we use the error of power spectral density between the estimated signal and the desired signal as the evaluation measure. Thus the a priori SNR is used to control the speech distortion weights in the frequency domain. In the experimental results, the proposed method yields better result in terms of MFCC distortion compared to the conventional method.

• Journal of KSNVE
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• v.7 no.1
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• pp.43-53
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• 1997

This paper investigated the practical use for measuring the structural intensity (power flow per width of cross section) in a uniform semi-infinite beam in flexural vibration. The structural intensity is obtained as a vector at a measurement point, One-dimensional structural intensity can be obtained from 4-point cross spectral measurement, or 2-point measurement on the assumption of far field. The measurement errors due to finite difference approximation and phase mismatch of accelerometers are examined. For precise measurements, it would be better to make the value of k$\delta$(wave number x space between accelerometers) between 0.5 and 1.0. Formulation of the relation between bending waves in structures and structural intensity makes it possible to separate the wave components by which one can get a state of the vibration field. Experimental results are obtained from 2- and 4-point measurement performed at 200mm (near field) and 400mm (far field) apart from excitation point in random excitation. the results are compared with the theoretical values and measured values of input power spectrum in order to verify the accuracy of structural intensity method, 2-point method is suggested as the practical structural intensity method.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.376-382
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• 2014

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.7 s.110
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• pp.638-647
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• 2006

Recently, the DFT-Spread OFDM has been studied for the PAPR reduction. However, the DFT-Spread OFDM produces more ICI and SCI problems than OFDM because phase offset mismatch of the DFT spreading code results from the random phase noise in the oscillator. In this paper, at first, phase noise influence on the DFT-Spread OFDM system is theoretically analyzed in terms of the BER performance. Then, the conventional ICI self-cancellation methods are discussed and two kinds of ICI self-cancellation methods are newly proposed. Lastly, a new DFT-Spread OFDM system which selectively adopts the ICI self-cancellation technique is proposed to resolve the interference problem and PAPR reduction simultaneously. Proposednew DFT-Spread OFDM system can minimize performance degradation caused by phase noise, and still maintain the low PAPR property. Among the studied methods, DFT-Spread OFDM with data-conjugate method or newly proposed symmetric data-conjugate method show the significant performance improvements, compared with the DFT-Spread OFDM without ICI self-cancellation schemes. The data-conjugate method is slightly better than symmetric data-conjugate method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.