• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.215-218
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• 2006

In this paper, a small size, $7{\times}6mm^2$, Low Noise Amplifier(LNA) using LTCC process was fabricated with multi-layer structure for 2.4GHz wireless LAN. The measured results demonstrate that the bandwidth is 130 MHz, and the operating frequency is from 2.39GHz to 2.52GHz. The power gain is above 7.3 dB in the operating frequency range and the gain flatness is 0.5 dB. The maximum S11 is -4 dB and the maximum S22 is -7.5 dB. The noise figure is less than 1.83 dB. The measured power gain, S11 and S22 were had poorer performance than the simulation results. The reason for this discrepancy is that the input and output matching was not performed exactly. However, the noise figure of the LTCC low noise amplifier is better than simulation result. It is found that it is possible to fabricate a LTCC low noise amplifier in a small size.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.28-31
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• 2004

This paper describe analysis active microstrip antenna with low noise amplifier at 900 MHz for mobile communication. The microstrip patch antenna is integrated with low noise amplifier on a permittivity 4.5 (Epoxy-FR4) and thickness of substrate 1.6 mm. Low noise amplifier is designed by using GaAs FETs. The analysis characteristics of antenna include return loss, input impedance, vswr, radiation pattarn, bandwidth and gain of antenna. Mesurement gain of antenna is shown 19.2435 dBi.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.12
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• pp.2269-2275
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• 2008

This paper examined the simulation results after applying not only spiral inductor's 3D EM simulation but also de-embedding technique to reduce the pad's RF effects. When calculating standard deviation with measurement results not only the gain at 0.5GHz${\sim}$4GHz but also noise figure at 1.8GHz${\sim}$4GHz, the simulation results includes de-embedded inductor' model improved gain deviation by 0.171 and noise figure deviation by 0.151 than the results from simulation with foundry inductor equivalent circuit models.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.451-454
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• 2002

In this paper, a low-noise amplifier is designed and fabricated using the HJFET for the reception of the Ku-band satellite broadcast signals. The optimum input and output reflection coefficients of each amplifier stage are obtained by the trade-off between the stable gain and the noise figure circle. The amplifier performance is simulated and optimized using a microwave CAD software. The designed amplifier is fabricated and tested. Results of the test show a gain of 17.0 dB, a gain flatness of less than $\pm$2.BdB, the noise figure of less than 1.0 dB, and the input and output reflection coefficient of less than -10 dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1579-1587
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• 2000

This paper presents the properties of the RF part in the receiving system based in IMT-2000 terminal technology. It mainly discuss the RF parameter performance of the receiving system for mobile telecommunication comparable to IS-98A and J-STD-018 specifications of commercially available CDMA and PCS, and is to anticipate the processing gain of the IMT-2000 receiving system, processing gain according to data processing rate, and terminal noise figure according to processing gain, relationship between noise figures according to Eb/Nt, Ioc. It is performed by such analysis method as CDMA and PCS receiving systems. Transmission bandwidth is n$\times$1.25 MHz(n=1, 3, 6, 9, 12) which is recommended by Qualcomm and NTT, the leading company in cdma 2000. Data transmission rate of IMT-2000 is classified into three cases as in moving vehicle environment of 144Kbps, outdoor pedestrian environment of 384Kbps, and indoor office environment of 2Mbps

• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1223-1229
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• 2004

A variable-gain low-voltage low noise amplifier MMIC operating at 5GHz frequency band is designed and implemented using the ETRI 0.5$\mu\textrm{m}$ GaAs MESFET library process. This low noise amplifier is designed to have the variable gain for adaptive antenna array combined in HIPERLAN/2. The feedback circuit of a resistor and channel resistance controlled by the gate voltage of enhancement MESFET is proposed for the variable-gain low noise amplifier consisted of cascaded two stages. The fabricated variable gain amplifier exhibits 5.5GHz center frequency, 14.7dB small signal gain, 10.6dB input return loss, 10.7dB output return loss, 14.4dB variable gain, and 2.98dB noise figure at V$\_$DD/=1.5V, V$\_$GGl/=0.4V, and V$\_$GG2/=0.5V. This low noise amplifier also shows-19.7dBm input PldB, -10dBm IIP3, 52.6dB SFDR, and 9.5mW power consumption.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.408-415
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• 2007

A switched-gain controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8\;GHz$ UWB system. In high gain mode, measurement shows a power gain of 12.5 dB, an input IP3 of 0 dBm, while consuming only 8.13 mA of current. In low gain mode, measurement shows a power gain of -8.7 dB, an input IP3 of 9.1 dBm, while consuming only 0 mA of current.

• ETRI Journal
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• v.46 no.4
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• pp.708-715
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• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.216-219
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• 2000

A Ka Band 3-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The MMIC LNA consists of two single-ended type amplication stapes and one balanced type amplication stage to satisfy noise figure characteristics and high gain and amplitude linearity. The 0.15um pHEMT has been used to provide a ultra low noise figure and high gain amplification. Series and Shunt feedback circuits were inserted to ensure high stability over frequency range of DC to 80 GHz. The size of designed MMIC LNA is 3100mm ${\times}$ 2400um(7.44$\textrm{mm}^2$). The on wafer measured noise figure of the MMIC LNA is less than 2.0 dB over frequency range of 22 GHz to 30 GHz.