• Korean Journal of Biological Psychiatry
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• v.23 no.3
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• pp.102-107
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• 2016

This review will summarize EEG studies of learning and memory based on frequency bands including theta waves (4-7 Hz), gamma waves (> 30 Hz) and alpha waves (7-12 Hz). Authors searched and reviewed EEG papers especially focusing on learning and memory from PubMed. Theta waves are associated with acquisition of new information from stimuli. Gamma waves are connected with comparing and binding old information in preexisting memory and new information from stimuli. Alpha waves are linked with attention. Eventually it mediates the learning and memory process. Although EEG studies of learning and memory still have controversial issues, the future EEG studies will facilitate clinical benefits by virtue of more developed and encouraging prospects.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.95-98
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• 1989

A new associative memory model using the SDF filter, one of the multiple filter for pattern recognition, is suggested in this paper. The SDF filter characteristics such as pattern classification lets the memorized patterns have orthogonal characteristics one another, so that enhances the associative memory's retrieval ability to the original pattern. The computer simulation shows that this new model is very useful in case that the imput patterns are seriously distorted and the cross-correlation between the memorized patterns is very high.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.445-458
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• 2007

This article presents a novel infrastructure for large-memory database processing using commodity hardware with operating system support. We exploit inexpensive PCs and a high-speed network capable of Remote Direct Memory Access (RDMA) operations to build a new memory hierarchy between fast volatile memory and slow disk storage. The new memory hierarchy guarantees a reasonable response time, and its storage size enables us to run large-memory database systems with little performance degradation. The proposed architecture has two main components: (1) a remote memory system inside the Linux kernel to manage other computers' memory pages efficiently and (2) a remote memory pager responsible for manipulating remote read/write operations on remote memory pages. We insist that the proposed architecture is practical enough to support the rigorous demands of commercial in-memory database systems by demonstrating the performance of publicly available main-memory databases (e.g., MySQL) on our prototyped system. The experimental results show very interesting results from the TPC-C benchmark.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.652-655
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• 2003

The human being receives a new information from outside and the information shows gradual oblivion with time. But it remains in memory and isn't forgotten for a long time if the information is read several times over. For example, we assume that we memorize a telephone number when we listen and never remind we may forget it soon, but we commit to memory long time by repeating. If the human being received new information with strong stimulus, it could remain in memory without recalling repeatedly. The moments of almost losing one's life in on accident or getting a stroke of luck are rarely forgiven. The human being can keep memory for a long time in spite of the limit of memory for the mechanism mentioned above. In this paper, we will make a model explaining that mechanism using a neural network Adaptive Resonance Theory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.7-14
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• 2017

Due to the recent advances in Phage-Change Memory (PCM) technologies, a new memory hierarchy of computer systems with PCM is expected to appear. In this paper, we present a new page replacement policy that adopts PCM as a high speed swap device. As PCM has limited write endurance, our goal is to minimize the amount of data written to PCM. To do so, we defer the eviction of dirty pages in proportion to their dirtiness. However, excessive preservation of dirty pages in memory may deteriorate the page fault rate, especially when the memory capacity is not enough to accommodate full working-set pages. Thus, our policy monitors the current working-set size of the system, and controls the deferring level of dirty pages not to degrade the system performances. Simulation experiments show that the proposed policy reduces the write traffic to PCM by 160% without performance degradations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.30-36
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• 1998

Memory management is one of the most important problems in implementing viterbi decoders. This paper introduces a novel traceback scheme for memory management of high-speed viterbi decoders. The new method balances the read and the write oeprations by inserting dummy write operations into the traceback process, resulting in simpler memory access schemes. It is suitable for VLSI implementation since it uses minimal memory requirements, it does not need global interconnections, and its address genration shceme for accessig memory contents is very simple.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.150-155
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• 2008

This paper is related to developing new Bit Error Rate (BER) simulator, Sam sung BER simulator (SBERS), in order to evaluate the link compliance and all kinds of effects of link compliance in a real environment. SBERS allows to generate transmit pulse accurately by using the various parameters, and obtain the eye diagram and bathtub curve, which represents the performance of link, by calculating the transmit pulse and the measured frequency response characteristics. SBERS give results as same as real environment after taking account of distribution and value of noise. To verify the accuracy of simulator, we derive the simulated and measured result and compare eye opening. The difference came out to be within 5% error. It is possible to estimate the real environment and design the transmitter and receiver circuit effectively using new BER simulator, SBERS.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10b
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• pp.324-329
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• 1992

A physical phenomenon is observed through analysis of the Hodgkin-Huxley's model that is, according to Maxwell field equations a fired neuron can yield magnetic fields. The magnetic signals are an output of the neuron as some type of information, which may be supposed to be the conscious control information. Therefore, study on neural networks should take the field effect into consideration. Accordingly, a study on the behavior of a unit neuron in the field is made and a new neuron model is proposed. A mathematical Memory-Learning Relation has been derived from these new neuron equations, some concepts of memory and learning are introduced. Two learning theorems are put forward, and the control mechanisms of memory are also discussed. Finally, a theory, i.e. Neural Electromagnetic(NEM) field theory is advanced.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.161-170
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• 2022

Recently, NAND-type flash memory has been regarded to be new promising storage media for large-scale database systems. For flash memory to be employed for that purpose, we need to reduce its expensive update cost caused by the inablity of in-place updates. To remedy such a drawback in flash memory, we propose a new flash-aware buffering scheme that enables virtual flushing of dirty pages. To this end, we slightly alter the tradional algorithms used for the logging scheme and buffer management scheme. By using the mechanism of virtual flushing, our proposed buffering scheme can efficiently prevent the frequenct occureces of page updates in flash storage. Besides the advantage of reduced page updates, the proposed viurtual flushing mechanism works favorably for shorneing a recocery time in the presense of failure. This is because it can reduce the time for redo actions during a recovry process. Owing to those two benefits, we can say that our scheme couble be very profitable when it is incorporated into cutting-edge flash-based database systems.

• Journal of KIISE
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• v.42 no.4
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• pp.434-441
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• 2015

Next generation memory technologies, which we denote as 'new memory', have both non-volatile and byte addressable properties. These characteristics are expected to bring changes to the conventional computer system structure. In this paper, we propose a fast boot technique for hybrid main memory architectures that have both new memory and DRAM. The key technique used for fast booting is write-tracking. Write-tracking is used to detect and manage modified data detection and involves setting the kernel region to read-only. This setting is used to trigger intentional faults upon modification requests. As the fault handler can detect the faulting address, write-tracking makes use of the address to manage the modified data. In particular, in our case, we make use of the MMU (Memory Management Unit) translation table. When a write occurs to the boot completed state, write-tracking preserves the original state of the modified address of the kernel region to a particular location, and execution continues. Upon booting, the fast booting process restores the preserved data to the original kernel region allowing rapid system boot-up. We develop the fast booting technique in an actual embedded board equipped with new memory. The boot time is reduced to less than half a second compared to around 15 seconds that is required for the original system.