• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.389-394
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• 2004

In this paper, according to characteristics of flash memory, a memory recycling method is proposed in order to decrease the necessary cost preventing performance degradation at the same time, In order to optimize the demanding costs, the new approach partitions the search space of flash memory segments into K segment groups, A method for memory space allocation, in addition, is proposed in order to satisfy the goal of even wearing over the total memory space, The optimized configuration of the proposed method is achieved through experiments, The fact that the newly proposed methods outperform the existing approaches regarding cost and performance is evaluated by simulations, Furthermore the experimental results demonstrate that the memory allocation method affects even wearing in great deal.

• International journal of advanced smart convergence
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• v.8 no.1
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• pp.9-17
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• 2019

In this article, we present a performance enhancement scheme for mobile applications by adopting persistent memory. The proposed scheme supports the deadline guarantee of real-time applications like a video player, and also provides reasonable performances for non-real-time applications. To do so, we analyze the program execution path of mobile software platforms and find two sources of unpredictable time delays that make the deadline-guarantee of real-time applications difficult. The first is the irregular activation of garbage collection in flash storage and the second is the blocking and time-slice based scheduling used in mobile platforms. We resolve these two issues by adopting high performance persistent memory as the storage of real-time applications. By maintaining real-time applications and their data in persistent memory, I/O latency can become predictable because persistent memory does not need garbage collection. Also, we present a new scheduler that exclusively allocates a processor core to a real-time application. Although processor cycles can be wasted while a real-time application performs I/O, we depict that the processor utilization is not degraded significantly due to the acceleration of I/O by adopting persistent memory. Simulation experiments show that the proposed scheme improves the deadline misses of real-time applications by 90% in comparison with the legacy I/O scheme used in mobile systems.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.369-372
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• 2002

To remedy both the degradation and saturation of the output voltages in the modified Dickson pump, a new multistage charge pump circuit is presented in this paper. Here using PMOS charge-transfer switches instead of NMOS ones eliminates the necessity of diode-configured output stage in the modified-Dickson pump, achieving the improved voltage pumping gain and its output voltages proportional to the stage numbers. Measurement indicates that VOUT/3VDD of this new pump circuit with two stages reaches to a value as high as 0.94V even with low VDD=1.0 V, strongly addressing that this scheme is very favorable at low-voltage memory applications.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.842-849
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• 2011

The transponder simulator designed to simulate the transponder of military satellite communication systems in the geostationary orbit is required to have time delay function, because of 250 ms delay time, when a radio wave transmits the distance of 36,000 km in free space. But, it is very difficult to develop 250 ms time delay device in the transponder simulator of 100 MHz bandwidth, due to unstable operation of FPGA, loss of memory data for the high speed rate signal processing. Up to date, bandwidth of the time delay device is limited to 45 MHz bandwidth. To solve this problem, we propose the new time delay techniques up to 100 MHz bandwidth without data loss. Proposed techniques are the low speed down scaling and high speed up scaling methods to read and write the external memory, and the matrix structure design of FPGA memory to treat data as high speed rate. We developed the satellite link simulator in 100 MHz bandwidth using the proposed new time delay techniques, implemented to the transponder simulator and verified the function of 265 ms time delay device in 100 MHz bandwidth.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.2
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• pp.101-109
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• 1998

In this paper, we implemented holographic optical memory systm which can store and reconstruct many images using new input and angular multiplexing method. In the new input method, phase infomation of input image is inputed in the recording material instead of brightness information. To do so, we represented the images, which captured with CCD camera or displayed on the computer monitor, on the liquid crystal television(LCTV) which removed polarizer/analyzer. Therefore, we can generate uniform input beam intensity regardless of the total brightness of input image, and apply the scheduled recording method. Also we can increase the intensity of input beam so reduce the recording time of input image. And reconstructedimage is acquired by transforming phase information into brightness information of image with analyzer. The incident angle of reference beam is acquired by Fourier transform of the binary phase hologram(BPH) which designed with SA algorithm on the LCTV. The proposed optical memory system is stable because the incident angle of the reference beam is controlled easy and electronically. We demonstreated optical experiment which store and reconstruct various type images in BaTiO$_{3}$ using proposed holographic memory system.

• Journal of the Korean Society of Propulsion Engineers
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• v.10 no.3
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• pp.99-108
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• 2006

Aerospace applications use pyrotechnic devices with many different functions. Functional shock, safety, overall system cost issue, and availability of new technologies, however, question the continued use of these mechanisms on aerospace applications. Release device is an important example of a task usually executed by pyrotechnic mechanisms. Many aerospace applications like satellite solar panels deployment or weather balloon separation need a release device. Several incidents, where pyrotechnic mechanisms could be responsible for spacecraft failure, have been encouraging new designs for these devices. The Frangibolt is a non explosive device which comprises a commercially available bolt and a small collar made of shape memory alloy (SMA) that replace conventional explosive bolt systems. This paper presents the modeling and simulation of Frangiblot by the change of bolt size and notch geometry. This analysis may contribute to improve the Frangibolt design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.411-421
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• 2002

In this paper, we present a new survivor path memory management method and a dedicated hardware architecture for the design of high-speed Viterbi decoders in modern digital communication systems. In the proposed method, a novel use of k-starting node number deciding circuits enables to acheive the immediate traceback of the merged survivor path from which we can decode output bits, and results in smaller survivor path memory size and processing delay time than the previously known methods. Also, in the proposed method, the survivor path memory can be constructed with ease using a simple standard dual-ported memory since one read-pointer and one write-pointer, that are updated at the same rate, are required for managing the survivor path: the previously known algorithms require either complex k-ported memory structure or k-times faster read capability than write. With a moderate hardware cost for immediate traceback capability the proposed method is superior to the previously known methods for high-speed Viterbi decoding.

• Journal of the Korea Society of Computer and Information
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• v.14 no.6
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• pp.1-10
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• 2009

Flash memory has the advantages of nonvolatile, low power consumption, light weight, and high endurance. This enables the flash memory to be utilized as a storage of mobile computing device such as PMP(Portable Multimedia Player). Potable device with a mass flash memory can store various multimedia data such as video, audio, or image. Typical index systems for mobile computer are inefficient to search a form of text like lyric or title. In this paper, we propose a new text index system, named EMTEX(Embedded Text Index). EMTEX has the following salient features. First, it uses a compression algorithm for embedded system. Second, if a new insert or delete operation is executed on the base table. EMTEX updates the text index immediately. Third, EMTEX considers the characteristics of flash memory to design insert, delete, and rebuild operations on the text index. Finally, EMTEX is executed as an upper layer of DBMS. Therefore, it is independent of the underlying DBMS. We evaluate the performance of EMTEX. The Experiment results show that EMTEX can outperform th conventional index systems such as Oracle Text and FT3.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.177-187
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• 1994

In the design of modern computer systems, the speed gap between the CPUs and DRAMs has been a major concern. To relieve this problem at a low cost, several new DRAM architectures have been proposed. This study is aimed at evaluating quantitatively the impact of the new DRAM architectures (synchronous DRAM. dual-RAS synchronous DRAM, and enhanced DRAM) on the memory system performance. We developed a cache and memory simulator and performed various experiments using the traces generated from four benchmark programs. The simulation results show that the new DRAM architectures offer a better performance than a conventional one by 5~30% in a low cost system and their improvement in a high performance system is less than 1%. However, for resonable multiprogramming workoads, additional performance improvement of about 10~28% is expected in a high performance system while 1~3% in a low cost system.