• 산업기술연구
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• 제15권
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• pp.51-62
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• 1995

Databases can crash due to various failures in computer systems. Recovery is a mechanism for restoring consistent data from damages caused by the by the failures and is an essential feature in database systems. This paper surveys recovery techniques for memory resident database systems. We first describe the basic architecture for memory resident database systems, and point out the main factors affecting their performance enhancement. Next, we explain the write-ahead logging(WAL), a recovery technique widely-used in most disk resident database systems, for easy understanding of basic recovery mechanisms. And then, we discuss some new concepts employed in memory resident database systems recovery. Finally, we present a representative memory resident database recovery technique, which is based on a special purpose hardware called HALO, as a case study.

• 한국통신학회논문지
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• 제21권8호
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• E2M - 전기 전자와 첨단 소재
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• 제13권12호
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• pp.6-9
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• 2000

Over the years of decades, the memory technology has progressed a long, marble way. As we have evidenced from the Intel's 1Kb DRAM in 1970 to the Gigabit era of 2000's, the road further ahead towards the Terabit era will be unfolded. The technology once perceived inconceivable is in realization today, and similarly roadblocks as we know of today mayvecome trivial issues for tomorrow. For the inquiring mind, the question is how the "puzzle"of tomorrow's memory technology is pieced-in today. The process will take place both in evolutionary and revolutionary ways. Among these, note-worthy are the changes in DRAM architecture and the cell process technology. In this paper, some technical approaches will be discussed to bring these aspects into a general overview and a per-spective with possibilities for the new memory technology will be presented.presented.

• ETRI Journal
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• 제26권1호
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• pp.21-26
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• 2004

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/($5{\times}$ constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.423-426
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• 2015

Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.17-20
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• 2000

Over the years of decades, the memory technology has progressed a long, marble way. As we have evidenced from the Intel’s 1Kb DRAM in 1970 to the Gigabit era of 2000’s, the road further ahead towards the Terabit era will be unfolded. The technology once perceived inconceivable is in realization today, and similarly roadblocks as we know of today may become trivial issues for tomorrow. For the inquiring mind, the question is how the “puzzle” of tomorrow’s memory technology is pieced-in today. The process will take place both in evolutionary and revolutionary ways. Among these, note-worthy are the changes in DRAM architecture and the cell process technology. In this paper, some technical approaches will be discussed to bring these aspects into a general overview and a perspective with possibilities for the new memory technology will be presented.

• ETRI Journal
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• 제45권2호
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• pp.304-317
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• 2023

With the rapid evolution of quantum computing, digital quantum simulations are essential for quantum algorithm verification, quantum error analysis, and new quantum applications. However, the exponential increase in memory overhead and operation time is challenging issues that have not been solved for years. We propose a novel approach that provides more qubits and faster quantum operations with smaller memory than before. Our method selectively tracks realized quantum states using a reduced quantum state representation scheme instead of loading the entire quantum states into memory. This method dramatically reduces memory space ensuring fast quantum computations without compromising the global quantum states. Furthermore, our empirical evaluation reveals that our proposed idea outperforms traditional methods for various algorithms. We verified that the Grover algorithm supports up to 55 qubits and the surface code algorithm supports up to 85 qubits in 512 GB memory on a single computational node, which is against the previous studies that support only between 35 qubits and 49 qubits.

• IMMUNE NETWORK
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• 제15권4호
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• pp.167-176
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• 2015

Macrophages are the main effector cells of innate immunity and are involved in inflammatory and anti-infective processes. They also have an essential role in maintaining tissue homeostasis, supporting tissue development, and repairing tissue damage. Until few years ago, it was believed that tissue macrophages derived from circulating blood monocytes, which terminally differentiated in the tissue and unable to proliferate. Recent evidence in the biology of tissue macrophages has uncovered a series of immune and ontogenic features that had been neglected for long, despite old observations. These include origin, heterogeneity, proliferative potential (or self-renewal), polarization, and memory. In recent years, the number of publications on tissue resident macrophages has grown rapidly, highlighting the renewed interest of the immunologists for these key players of innate immunity. This minireview aims to summarizing the new current knowledge in macrophage immunobiology, in order to offer a clear and immediate overview of the field.

• 한국지능시스템학회논문지
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• 제11권4호
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• pp.340-346
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• 2001

본 논문은 GBAM (general bidirectional associative memory) 모델을 위한 새로운 설계방법을 제시한다. GBAM 모델에 대한 이론적 고찰을 바탕으로, GBAM 기방 양방향 연상 메모리의 설계 문제가 GEVP (generalized eigenvalue problem)로 불리는 최적화 문제로 표현될 수 있음을 밝힌다. 설계 과정에서 등장하는 GEVP 문제들은 최근에 개발된 내부점 방법에 의하여 주어진 허용 오차 이내에서 효과적으로 풀릴 수 있으므로, 본 논문에서 확립된 설계 절차는 매우 실용적이다. 제안된 설계 절차에 대한 적용 가능성은 관련 연구에서 고려되었던 간단한 설계 예제를 통하여 예시된다.

• 한국멀티미디어학회논문지
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• 제9권12호
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• pp.1617-1627
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• 2006

The concept of middleware for digital TV receivers is not new one. Using middleware for digital TV development has a number of advantages. It makes it easier for manufacturers to hide differences in the underlying hardware. It also offers a standard platform for application developers. Digital TV middleware enables set-top boxes(STBs) to run video, audio, and applications. The main concern of digital TV middleware is now to reduce its memory usage because most STBs in the market are small footprint. In this paper, we propose several ideas about how to reduce the required memory size on the runtime area of DTV middleware using a new native process technology. Our proposed system has two components; the Efficient Native Process Module, and Enhanced Native Interface APIs for concurrent native modules. With our approach, the required memory reduced from 50% up to 75% compared with the traditional approach. It can be suitable for low end STBs of very low hardware limitation.