• ETRI Journal
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• v.9 no.1
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• pp.31-36
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• 1987

전자회로를 시뮬레이션하려면 게이트나 트랜지스터의 연결상태(netlist)를 입력시켜야 한다. EDAS_P시스팀의 SCHEX_P라는 tool은 그림으로 표현된 전자회로도로부터 연결상태를 추출하고, 계층 설계된 구조를 풀어 게이트나 트랜지스터만으로 표현된 netlist를 만든 후 시뮬레이터가 받아들일 수 있는 형식으로 문장을 재조립한다. 본고에서는 이 과정을 요약하여 설명 하고자 한다.

• International Journal of Control, Automation, and Systems
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• v.3 no.3
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• pp.493-501
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• 2005

A power plant simulation tool ('PowerSim') has been developed with 10 years experience from the development of a plant simulator for efficient modeling of a power plant. PowerSim is the first developed tool in Korea for plant simulation with various plant component models, instructor station function and the Graphic Model Builder (GMB). PowerSim is composed of a graphic editor using general purpose design software, a netlist converter, component models, the scheduler, Instructor Station and an executive. The graphic editor generates a netlist that shows the connection status of the various plant components from the Simdiagram, which is drawn by Icon Drag method supported by GUI environment of the PowerSim. Netlist Converter normalizes the connection status of the components. Scheduler makes scheduling for the execution of the device models according to the netlist. Therefore, the user makes Simdiagram based on the plant Pipe and Instrument Drawing (P&ID) and inputs the plant data for automatic simulating execution. This paper introduces Graphic Model Builder (GMB), instructor station, executive and the detailed introduction of thermal-hydraulic modeling. This paper will also introduce basic ideas on how the simulation Diagram, based on netlist generated from general purpose design software, is made and how the system is organized. The developed tool has been verified through the simulation of a real power plant.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.1025-1032
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• 1998

In this paper, the PLD design tool which realizes a digital circuit as PLD, by using EDIF netlist of the digital circuit designed at OrCAD have been developed. This paper is proposed the following algorithms: JIE(Joined Information Extractor) which extracts the connecting information between both cells in order to realize the digital circuit as PLD using the EDIF netlist, FND(Feedback Node Detector) which look into whether feedback exists or not, BEG(Boolean Equation Generator) which generates a boolean equation, and so on. Also, this paper is developed auto-select function which selects the PLD element with consideration of number of I/O variables of the minimized boolean equation, and algorithm generation JEDEC file of GAL6001 and GAL6002, having a forms of EPLD which is bigger than PLD.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.21-28
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• 1998

In this paper, we propose an efficient linear ordering algorithm, called LIME, for netlist partitioning. LIME incrementally merges two segments which are selected based on the proposed cost function until only one segment remains. The final resultant segment then corresponds to the linear ordering. LIME also runs extremely fast, because it exploits sparsity of netlist. Compared to the earlier work, the proposed algorithm is eight times faster in producing linear ordering and yields an average of 17% improvement for the multi-way scaled cost partitioning.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.10a
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• pp.90-94
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• 1998

한국전력공사 전력연구원은 10년간의 시뮬레이터 개발 경험을 바탕으로 Windows(NT)환경의 시뮬레이터 개발 툴인 Powersim을 독자적으로 개발하고 이를 이용하여 화력발전소 DCS(Distributed Control System) 검증용 시뮬레이터를 개발하고 있다. PowerSim은 GMB(Graphic Model Builder)를 갖춘 국내 최초의 시뮬레이터 개발툴로 다양한 발전소 기기모델과 강사조작반기능을 갖추고 있다. PowerSim은 완벽한 GUI (Graphic User Interface)환경을 지원하여 User가 Icon Drag 방식으로 시뮬레이션 도면(SimDiagram)을 그리면 그래픽 에디터에서 출력된 각종 기기의 접속상태를 나타내는 Netlist를 변환기가 처리하여 기기의 연결상태를 정규화하고 Scheduler는 기기모델(일종의 Subroutine)을 Netlist에 맞게 Scheduling하여 Executive에서 실행 가능한 형태로 만드는 모든 과정이 자동화되어 있다. 따라서, 개발자는 발전소 P&ID(Pipe and Instrument Drawing)에 기초하여 Simdiagram을 그리고 발전소 데이터를 입력하는 것만으로 실시간 시뮬레이터를 구현할 수 있다. 본 논문에서는 PowerSim의 개요와 GMB(Graphic Model Builder) 및 강사조작반에 적용된 GUI 환경과 실시간 Executive에 대해 다룬다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.416-419
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• 2011

본 논문에서는 XILINX의 합성 과정에서 생성되는 XDL 설계 데이터를 분석해서, 그로부터 verilog 네트리스트를 생성하는 소프트웨어의 개발에 관한 내용이다. 이 소프트웨어는 XILINX 용 P&R 소프트웨어, 논리 합성 소프트웨어의 개발, 또는 FPGA 상에서 특정 컴포넌트의 위치를 파악해냄으로써 FPGA 상에서 SEU 오류의 위치를 검출하는데 보조적으로 사용할 수 있다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.1010-1018
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• 1988

This paper proposes a MOS circuit extractor which extracts a netlist from the hierarchical mask information, for the verification tools. To utilize the regularity and the simple representation of the hierarchical circuit, and to reduce the debug cycle of design, verification, and modification, we propose a hierarvhical and incremental circuit extraction algorithm. In flat circuit extraction stage, the multiple storage quad tree is used as an internal data structure. Incremental circuit extraction using the hierarchical structure is made possible, to reduce the re-extraction time of the modified circuit.