• Korean Journal of Optics and Photonics
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• v.19 no.3
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• pp.193-198
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• 2008

A novel refractive index sensor, which consists of polymer channel waveguide overlaid with $TiO_2$ thin film, is demonstrated. To evaluate the fabricated sensor, we measured the polarimetric interference induced by concentration change of injected glycerol solution. Our experimental results show that thicker $TiO_2$ film improves the sensitivity of the polarimetric interferometer. For the fabricated waveguide with a 20 nm thick $TiO_2$ film, the measured index change to lead phase variation of $2{\pi}$ is $1.8{\times}10^{-3}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.45-45
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• 2007

Capacitors among the embedded passive components are most widely studied because they are the major components in terms of size and number and hard to embed compared with resistors and inductors due to the more complicated structure. To fabricate a capacitor-embedded PCB for in-line process, it is essential to adopt a low temperature process (<$200^{\circ}C$). However, high dielectric materials such as ferroelectrics show a low permittivity and a high dielectric loss when they are processed at low temperatures. To solve these contradicting problems, we studied BMN materials as a candidate for dielectric capacitors. processed at PCB-compatible temperatures. The morphologies of BMN thin films were investigated by AFM and SEM equipment. The electric properties (C-F, I-V) of Pt/BMN/Cu/polymer were evaluated using an impedance analysis (HP 4194A) and semiconductor parameter analyzer (HP4156A). $Bi_2Mg_{2/3}Nb_{4/3}O_7$(BMN) thin films deposited on copper clad laminate substrates by sputtering system as a function of Ar/$O_2$ flow rate at room temperature showed smooth surface morphologies having root mean square roughness of approximately 5.0 nm. 200-nm-thick films deposited at RT exhibit a dielectric constant of 40, a capacitance density of approximately $150\;nF/cm^2$, and breakdown voltage above 6 V. The crystallinity of the BMN thin films was studied by TEM and XRD. BMN thin film capacitors are expected to be promising candidates as embedded capacitors for printed circuit board (PCB).

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.17-21
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• 2007

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.253-256
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• 2017

A thin Te interlayer was applied to a Ni/n-InGaAs contact to reduce the contact resistance between Ni-InGaAs and n-InGaAs. A 5-nm-thick Te layer was first deposited on a Si-doped n-type $In_{0.53}Ga_{0.47}As$ layer, followed by in situ deposition of a 30-nm-thick Ni film. After the formation of the Ni-InGaAs alloy by rapid thermal annealing at $300^{\circ}C$ for 30 s, the extracted specific contact resistivity (${\rho}_c$) reduced by more than one order of magnitude from $2.86{\times}10^{-4}{\Omega}{\cdot}cm^2$ to $8.98{\times}10^{-6}{\Omega}{\cdot}cm^2$ than that of the reference sample. A thinner Ni-InGaAs alloy layer with a better morphology was obtained by the introduction of the Te layer. The improved interface morphology and the graded Ni-InGaAs layer formed at the interface were believed to be responsible for ${\rho}_c$ reduction.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.5
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• pp.411-416
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• 2006

A new reading technology for the ultra-high density data storage device utilizing AFM technology was proposed and its experimental results were discussed in this paper. For the experiments, an about $2{\mu}m$ thick conductive polymer layer was spin-coated on the heavily doped n-type Si wafer and an about $0.1{\mu}m$ thick PMMA layer was also been spin-coated on it. After then, the $5{\times}5$ memory way was fabricated by making indents on the surface of the wafer with the heated AFM tip, and the data reading was performed by scanning the surface with the tip biased at 10 V and the measuring the current flowing out at the end of the tip. The experimental results clearly showed that the new data reading technology worked superbly. The current measured was about 0.92 pA at the cell with the indent, and it was not only below 0.31 pA at the cell without the indent, but also at the cell where the indent was erased.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.16-22
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• 2008

We fabricated thermally-evaporated 10 nm-Ni/30 nm and 70 nm Poly-Si/200 nm-$SiO_2/Si$ structures to investigate the thermal stability of nickel silicides formed by rapid thermal annealing(RTA) of the temperature of $300{\sim}1100^{\circ}C$ for 40 seconds. We employed for a four-point tester, field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), high resolution X-ray diffraction(HRIXRD), and scanning probe microscope(SPM) in order to examine the sheet resistance, in-plane microstructure, cross-sectional microstructure evolution, phase transformation, and surface roughness, respectively. The silicide on 30 nm polysilicon substrate was stable at temperature up to $900^{\circ}C$, while the one on 70 nm substrate showed the conventional $NiSi_2$ transformation temperature of $700^{\circ}C$. The HRXRD result also supported the existence of NiSi-phase up to $900^{\circ}C$ for the Ni silicide on the 30 nm polysilicon substrate. FE-SEM and TEM confirmed that 40 nm thick uniform silicide layer and island-like agglomerated silicide phase of $1{\mu}m$ pitch without residual polysilicon were formed on 30 nm polysilicon substrate at $700^{\circ}C\;and\;1000^{\circ}C$, respectively. All silicides were nonuniform and formed on top of the residual polysilicon for 70 nm polysilicon substrates. Through SPM analysis, we confirmed the surface roughness was below 17 nm, which implied the advantage on FUSI gate of CMOS process. Our results imply that we may tune the thermal stability of nickel monosilicide by reducing the height of polysilicon gate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.303-310
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• 2008

We fabricated hydrogenated amorphous silicon(a-Si:H) 140 nm thick film on a $180\;nm-SiO_2/Si$ substrate with an inductively-coupled plasma chemical vapor deposition(ICP-CVD) equipment at $250^{\circ}C$. Moreover, 30 nm-Ni film was deposited with a thermal-evaporator sequently. Then the film stack was annealed to induce silicides by a rapid thermal annealer(RTA) at $200{\sim}500^{\circ}C$ in every $50^{\circ}C$ for 30 minuets. We employed a four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), and scanning probe microscope(SPM) in order to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure evolution, and surface roughness, respectively. We confirmed that nano-thick high resistive $Ni_3Si$, mid-resistive $Ni_2Si$, and low resistive NiSi phases were stable at the temperature of <300, $350{\sim}450^{\circ}C$, and >$450^{\circ}C$, respectively. Through SPM analysis, we confirmed the surface roughness of nickel silicide was below 12 nm, which implied that it was superior over employing the glass and polymer substrates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.192-192
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• 2009

We have successfully demonstrated the inkjet printing process to fabricate $Al_2O_3$ thick films without a high temperature sintering process. A single solvent system had a coffee ring pattern after printing of $Al_2O_3$ dot, line and area. In order to fabricate the smooth surface of $Al_2O_3$ thick film, we have introduced a co-solvent system which has nano-sized $Al_2O_3$ powders in the mixture of Ethylene glycol monomethyl ester and Di propylene glycol methyl ether. This co-solvent system approached a uniform and dense deposition of $Al_2O_3$ powders on the substrate. The packing density of inkjet-printed $Al_2O_3$ films is more than 70% which is very high compared to the value obtained from the films synthesized by other conventional methods such as casting processes. The characterization of the inkjet-printed $Al_2O_3$ films has been implemented to investigate its thickness and roughness. Also the dielectric loss of the films has been measured to understand the feasibility of its application to 3D integration package substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.483-491
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• 2017

The interdigitated germanium (Ge) meta-lsemiconductor-metal (MSM) photodetectors (PDs) with and without an $SiO_2$ anti-reflection (AR) layer was fabricated, and the effect of $SiO_2$ AR layer on their optoelectronic response properties were investigated in detail. The lowest reflectance of 15.6% at the wavelength of 1550 nm was obtained with a $SiO_2$ AR layer with a thickness of 260 nm, which was in a good agreement with theoretically calculated film thickness for minimizing the reflection of Ge surface. The Ge MSM PD with 260 nm-thick $SiO_2$ AR layer exhibited enhanced device performance with the maximum values of responsivity of 0.65 A/W, the quantum efficiency of 52.2%, and the detectivity of $2.49{\times}10^9cm\;Hz^{0.5}W^{-1}$ under the light illumination with a wavelength of 1550 nm. Moreover, time-dependent switching analysis of Ge MSM PD with 260 nm- thick $SiO_2$ AR layer showed highest on/off ratio with excellent stability and reproducibility. All this investigation implies that 260 nm-thick $SiO_2$ AR layer, which is effective in the reduction in the reflection of Ge surface, has a great potential for Ge based optoelectronic devices.

• Korean Journal of Materials Research
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• v.26 no.8
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• pp.417-421
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• 2016

We improve the energy conversion efficiency (ECE) of a dye sensitized solar cell (DSSC) by preparing a working electrode (WE) with localized surface plasmon resonance (LSPR) by inducing Au thin films with thickness of 0.0 to 5.0 nm, deposited via sputtering. Field emission scanning electron microscopy and atomic force microscopy were used to characterize the microstructure of the blocking layer (BL) of the Au thin films. Micro-Raman measurement was employed to confirm the LSPR effect, and a solar simulator and potentiostat were used to evaluate the photovoltaic properties, including the impedance and the I-V of the DSSC of the Au thin films. The results of the microstructural analysis confirmed that nano-sized Au agglomerates were present at certain thicknesses. The photovoltaic results show that the ECE reached a value of 5.34% with a 1-nm thick-Au thin film compared to the value of 5.15 % without the Au thin film. This improvement was a result of the increase in the LSPR of the $TiO_2$ layer that resulted from the Au thin film coating. Our results imply that the ECE of a DSSC may be improved by coating with a proper thickness of Au thin film on the BL.