• Title/Summary/Keyword: nano-scale junctions

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Using Electron-beam Resists as Ion Milling Mask for Fabrication of Spin Transfer Devices

  • Nguyen Hoang Yen Thi;Yi, Hyun-Jung;Shin, Kyung-Ho
    • Journal of Magnetics
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    • v.12 no.1
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    • pp.12-16
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    • 2007
  • Magnetic excitation and reversal by a spin polarized current via spin transfer have been a central research topic in spintronics due to its application potential. Special techniques are required to fabricate nano-scale magnetic layers in which the effect can be observed and studied. This work discusses the possibility of using electron-beam resists, the nano-scale patterning media, as ion milling mask in a subtractive fabrication method. The possibility is demonstrated by two resists, one positive tone, the ZEP 520A, and one negative tone, the ma-N2403. The advantage and the key points for success of this process will be also addressed.

70nm NMOSFET Fabrication with Ultra-shallow $n^{+}-{p}$ Junctions Using Low Energy $As_{2}^{+}$ Implantations (낮은 에너지의 $As_{2}^{+}$ 이온 주입을 이용한 얕은 $n^{+}-{p}$ 접합을 가진 70nm NMOSFET의 제작)

  • Choe, Byeong-Yong;Seong, Seok-Gang;Lee, Jong-Deok;Park, Byeong-Guk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.2
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    • pp.95-102
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    • 2001
  • Nano-scale gate length MOSFET devices require extremely shallow source/drain eftension region with junction depth of 20∼30nm. In this work, 20nm $n^{+}$-p junctions that are realized by using this $As_{2}^{+}$ low energy ($\leq$10keV) implantation show the lower sheet resistance of the $1.0k\Omega$/$\square$ after rapid thermal annealing process. The $As_{2}^{+}$ implantation and RTA process make it possible to fabricate the nano-scale NMOSFET of gate length of 70nm. $As_{2}^{+}$ 5 keV NMOSFET shows a small threshold voltage roll-off of 60mV and a DIBL effect of 87.2mV at 100nm gate length devices. The electrical characteristics of the fabricated devices with the heavily doped and abrupt $n^{+}$-p junctions ($N_{D}$$10^{20}$$cm^{-3}$, $X_{j}$$\leq$20nm) suggest the feasibility of the nano-scale NMOSFET device fabrication using the $As_{2}^{+}$ low energy ion implantation.

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Improvement of Thermal Stability of Ni-Silicide Using Vacuum Annealing on Boron Cluster Implanted Ultra Shallow Source/Drain for Nano-Scale CMOSFETs

  • Shin, Hong-Sik;Oh, Se-Kyung;Kang, Min-Ho;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.4
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    • pp.260-264
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    • 2010
  • In this paper, Ni silicide is formed on boron cluster ($B_{18}H_{22}$) implanted source/drains for shallow junctions of nano-scale CMOSFETs and its thermal stability is improved, using vacuum annealing. Although Ni silicide on $B_{18}H_{22}$ implanted Si substrate exhibited greater sheet resistance than on the $BF_2$ implanted one, its thermal stability was greatly improved using vacuum annealing. Moreover, the boron depth profile, using vacuum post-silicidation annealing, showed a shallower junction than that using $N_2$ annealing.

70nm NMOSFET fabrication with ultra-shallow n+-p junctions using low energy As<+>(2) implantations (낮은 에너지의 As<+>(2) 이온 주입을 이용한 얕은 n+-p 접합을 가진 70nm NMOSFET의 제작)

  • Lee, Jong Deok;Lee, Byeong Guk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.2
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    • pp.9-9
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    • 2001
  • Nano-scale의 게이트 길이를 가지는 MOSFET소자는 접합 깊이가 20∼30㎚정도로 매우 얕은 소스/드레인 확장 영역을 필요로 한다. 본 연구에서는 $As₂^ +$ 이온의 10keV이하의 낮은 에너지 이온 주입과 RTA(rapid thermal annealing)공정을 적용하여 20㎚이하의 얕은 접합 깊이와 1.O㏀/□ 이하의 낮은 면저항 값을 가지는 $n ^+$-p접합을 구현 하였다. 이렇게 형성된 $n^ +$-p 접합을 nano-scale MOSFET소자 제작에 적용 시켜서 70㎚의 게이트 길이를 가지는 NMOSFET을 제작하였다. 소스/드레인 확장 영역을 $As₂^ +$ 5keV의 이온 주입으로 형성한 100㎚의 게이트 길이를 가지는 NMOSFET의 경우, 60mV의 낮은 $V_ T$(문턱 전압감소) 와 87.2㎷의 DIBL (drain induced barrier lowering) 특성을 확인하였다. $10^20$$㎝^ -3$이상의 도핑 농도를 가진 abrupt한 20㎚급의 얕은 접합, 그리고 이러한 접합이 적용된 NMOSFET소자의 전기적 특성들은 As₂/sup +/의 낮은 에너지의 이온 주입 기술이 nano-scale NMOSFET소자 제작에 적용될 수 있다는 것을 제시한다.

Molecular Dynamics (MD) Simulation of Ultra-shallow Ion Implantation with a Modified Recoil Ion Approximation

  • Ohseob Kwon;Kim, Kidong;Jihyun Seo;Taeyoung Won
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.735-738
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    • 2003
  • In this paper, we report a molecular dynamics (MD) simulation of the ion implantation for nano-scale devices with ultra-shallow junctions. In order to model the profile of ion distribution in nanometer scale, the molecular dynamics with a damage model has been employed. As an exemplary case, we calculate the dopant profile during the ion implantation of B, As, and Ge.

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Synthesis and Characterization of DNA-Templated Nanostructures: Toward Molecular Electronics

  • Lee, Jeong-Gyu
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.92.1-92.1
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    • 2013
  • Molecular electronics has been the subject of intese research for many years because of the fundamental interest in molecular charge transport and potential applications, such as (bio)nanosensors and molecular memory devices. Molecular electronics requires a method for making reliable eletrical contacts to singlemolecules. To date, several approaches have been reported: scanning-probe microscopy, mechanical break junctions, nano patterning, and direct deposition of electrode on a self-assembled monolayers. However, most methods are laborious and difficult for large-scale application and more importantly, cannot control the number of moleucles in the junction. Recently, DNA has been used as a template for metallic nanostructures (e.g., Ag, Pd, and Au nanowires) through DNA metallization process. Furthermore, oligodeoxynucleotides have been tethered to organic molecules by using conventional organic reactions. Collectively, these techniques should provide an efficient route toward reliable and reproducible molecular electronic devices with large-scale fabrication. Therefore, I will present a paradigm for the fabrication of moleuclar electronic devices by using micrometer-sized DNA-singe organic molecule and DNA triblock structures.

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