• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.484-485
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• 2011

반사방지(Anti-Reflection, AR) 특성은 태양전지, LED, 광검출기 등의 광전소자와 디스플레이의 효율과 투과도를 향상시키기 위해 적용되고 있다. 또한 최근에 네비게이션, 스마트폰의 보급 증가로 인해 소형 디스플레이에 지문방지와 동시에 반사방지 기능을 갖는 필름이 사용되고 있다. 현재 적용되고 있는 반사방지 필름은 다층박막 코팅으로 형성된 필름[1]으로 생산단가와 박막의 내구성 및 신뢰성에 문제점을 가지고 있다. 이런 문제점을 해결하기 위해 나노구조로 제작 되는 반사방지 필름에 관한 연구가 활발히 진행되고 있다[2]. 나노구조로 형성된 반사방지 구조는 moth-eye 구조라고 하며, 기본 원리는 원뿔 형태를 형성된 나노 구조를 통해 공기와 나노구조 사이의 유효 굴절률을 서서히 변화시켜 반사를 줄이는 것이다. 그러므로 moth-eye 나노구조는 파장 이하의 pitch와 파장 크기의 높이를 갖도록 구조가 제작되어야 한다[3]. Photo-lithography[4], e-beam lithography[5], interference lithography[6], dip-pen nanolithography[7], hybrid nano-patterning lithography[8] 등 여러 가지 방법으로 나노 구조를 제작하고 있으나, 네비게이션이나 스마트폰 등에 적용될 수 있는 대면적으로 제작하기 위해서는 roll-to-roll printing과 같은 대면적 공정을 이용하여 제작하는 것이 필요하다. 본 논문에서는 원통형 알루미늄 rod에 양극산화를 통해 다공성 AAO(anode aluminium oxide) template를 제작하고, roll-to-roll printing 기술을 사용하여 moth-eye 나노구조를 갖는 반사방지 필름을 제작하는 것에 대해 기술하였다.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.98-99
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• 2007

This study has successfully demonstrated the direct fabrication of polymer resistors using ink-jet printing technology as an alternative patterning to traditional photolithography. The polymer resistors were fabricated just by two layer processes using a ink-jet printer (DMP-2800, Fujifilm Dimatix). First, resistive materials was patterned by a ink-jet printing with the desired width and length. Next, resistor fabrication was completed by printing metal contact pads on the both sides of the polymer resistor. We used poly (3,4-ethylene dioxythiophene) poly(styrenesulfonate)(PEDOT:PSS) for the resistor material and a nano-sized silver colloid for the metal contact pads. We characterized the electrical properties of PEDOT:PSS by measuring sheet resistance and specific resistance on a glass substrate. From analysis of the measured resistances, the electrical resistances of the polymer resistors linearly increased as a function of printed width and length of resistors. The accuracy of the fabricated polymer resistor showed about $0.6{\sim}2.5%$ error for the same dimensions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.514-514
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• 2007

1차원 구조를 갖는 나노 와이어들은 나노 소자를 구현하기 위한 building-block으로 많은 과학자들의 주목을 받고 있고 또한 연구되고 있다. 하지만 그것을 정확하게 위치시키고 일정한 간격으로 정렬시키기 위한 기술 개발은 아직도 해결해야 할 큰 과제로 남아 있다. 이 논문에서, 우리는 ahsing 기술과 표면 패터닝 기술을 이용하여 대면적의 실리콘웨이퍼 위에 DNA(deoxyribonucleic acid)를 기반으로 한 금 나노 와이어를 정확하게 위치시키고 일정한 간격으로 정렬시킬 수 있는 새로운 제어 기술을 제안한다. 먼저 우리는 포토 리소그래피 공정과 $O_2$ 플라즈마 ashing 기술을 이용하여 선폭을 100 nm로 감소 시켰다. 그리고 자기조립단분자막 (self-assembled monolayers; SAMs) 방법과 lift-off 공정을 반복함으로서 1-octadecyltrichlorosilane(OTS) 층과 aminopropylethoxysilane(APS) 층을 형성하였다. 마지막으로 DNA 용액을 샘플 표면 위에 도포하고 분자 빗질 방법으로 DNA를 한 방향으로 정렬 시켰고 금 나노입자 용액을 처리하였다. 그 결과 금 나노 와이어는 $10{\mu}m$ 간격으로 일정하게 정열 되었고, APS 층에만 정확하게 정렬되었다. 우리는 금 나노 와이어를 관찰하기 위하여 원자간력 현미경 (Atomic Force Microscope AFM)을 사용하였다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.593-597
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• 2005

FIB equipment can perform sputtering and chemical vapor deposition simultaneously. It is very advantageously used to fabricate a micro structure part having 3D shape because the minimum beam size of ${\phi}$ 10nm and smaller is available. Currently FIB is not being applied in the fabrication of this micro part because of some problems to redeposition and charging effect of the substrate causing reduction of accuracy with regards to shape and productivity. Furthermore, the prediction of the material removal rate information should be required but it has been insufficient for micro part fabrication. The paper have the targets that are FIB-CVD characteristic analysis and minimum line pattern resolution achievement fur 3D micro fabrication. We make conclusions with the analysis of the results of the experiment according to beam current, pattern size and scanning parameters. CVD of 8 pico ampere shows superior CVD yield but CVD of 1318 pico ampere shows the pattern sputtered. And dwell time is dominant parameter relating to CVD yield.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.11
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• pp.186-194
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• 2004

In this research, microfabrication technique using localized electrochemical deposition (LECD) with ultra short pulses is presented. Electric field is localized near the tool tip end region by applying a few hundreds of nano second pulses. Pt-Ir tip is used as a counter electrode and copper is deposited on the copper substrate in 0.5 M CuSO$_4$ and 0.5 M H$_2$SO$_4$ electrolyte. The effectiveness of this technique is verified by comparison with LECD using DC voltage. The deposition characteristics such as size, shape, surface, and structural density according to applied voltage and pulse duration are investigated. The proper condition is selected from the results of the experiments. Micro columns less than 10 $\mu$m in diameter are fabricated using this technique. The real 3D micro structures such as micro pattern and micro spring can be fabricated by this method. It is suggested that presented method can be used as an easy and inexpensive method for fabrication of microstructure with complex shape.

• Journal of the Korean institute of surface engineering
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• v.56 no.2
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• pp.115-124
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• 2023

Anodization is an electrochemical process that electrochemically converts a metal surface into an oxide layer, resulting in enhanced corrosion resistance, wear resistance, and improved aesthetic appearance. Local anodization, also known as selective anodization, is a modified process that enables specific regions or patterns on the metal surface to undergo anodization instead of the entire surface. Several methods have been attempted to produce oxide layers via localized anodic oxidation, such as using a mask or pre-patterned substrate. However, these methods are often intricate, time-consuming, and costly. Conversely, the direct writing or patterning approach is a more straightforward and efficient way to fabricate the oxide layers. This review paper intends to enhance our comprehension of local anodization and its potential applications in various fields, including the development of nanotechnologies. The application of anodization is promising in surface engineering, where the anodic oxide layer serves as a protective coating for metals or modifies the surface properties of materials. Furthermore, anodic oxidation can create micro- and nano-scale patterns on metal surfaces. Overall, the development of efficient and cost-effective anodic oxidation methods is essential for the advancement of various industries and technologies.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.6
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• pp.345-351
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• 2019

Recently, ink-jet printing technology has been applied for various industries such as semiconductor, display, ceramic tile decoration. Ink-jet printing has advantages of high resolution patterning, fast printing speed, high ink efficiency and many attempts have been made to apply functional materials with excellent physical and chemical properties for the ink-jet printing process. Due to these advantages, research scope of ink-jet printing is expanding from conventional two-dimensional printing to three-dimensional printing. In order to expand the application of ink-jet printing, it is necessary to optimize the rheological properties of the ink and the interaction with the substrate. In this study, photo curable ceramic complex ink containing nano silica particles were synthesized and its printability was characterized. Contact angle of the photo curable silica ink were modified by control of the ink composition and the surface property of the substrate. Effects of contact angle on printing resolution and three-dimensional printability were investigated in detail.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.433-433
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• 2012

As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

• Korean Journal of Materials Research
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• v.15 no.10
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• pp.626-631
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• 2005

GaN-related compound semiconductors were grown on the corrugated interface substrate using a metalorganic chemical vapor deposition system to increase the optical power of white LEDs. The patterning of substrate for enhancing the extraction efficiency was processed using an inductively coupled plasma reactive ion etching system and the surface morphology of the etched sapphire wafer and that of the non-etched surface were investigated using an atomic force microscope. The structural and optical properties of GaN grown on the corrugated interface substrate were characterized by a high-resolution x-ray diffraction, transmission electron microscopy, atomic force microscope and photoluminescence. The roughness of the etched sapphire wafer was higher than that of the non-etched one. The surface of III-nitride films grown on the hemispherically patterned wafer showed the nano-sized pin-holes that were not grown partially. In this case, the leakage current of the LED chip at the reverse bias was abruptly increased. The reason is that the hemispherically patterned region doesn't have (0001) plane that is favor for GaN growth. The lateral growth of the GaN layer grown on (0001) plane located in between the patterns was enhanced by raising the growth temperature ana lowering the reactor pressure resulting in the smooth surface over the patterned region. The crystal quality of GaN on the patterned substrate was also similar with that of GaN on the conventional substrate and no defect was detected in the interface. The optical power of the LED on the patterned substrate was $14\%$ higher than that on the conventional substrate due to the increased extraction efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.