• Journal of the Korean Physical Society
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• v.73 no.12
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• pp.1895-1898
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• 2018

The mechanical properties of Al, Ti, Fe, and Cu metals p-type Si, and n-type Si were investigated by using coincidence Doppler broadening (CDB) positron annihilation spectroscopy. The samples in this experiment were irradiated by using X-rays at generating powers for up to 9 kW. The data taken after the irradiation showed all the characteristic features predicted from defects with vacancies. The S parameter values of the metals were generally less than those of semiconductors such as p-type Si and n-type Si. The relationship between n-type Si and p-type Si were more affected when n-type Si rather than p-type Si was irradiated with X-rays.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.3
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• pp.83-90
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• 2019

In this paper, Mg-doped AlN epilayers for power semiconductor devices are grown by mixed-source hydride vapor phase epitaxy. Magnesium is used as p-type dopant material in the grown AlN epilayer. The AlN epilayers on the GaN-templated sapphire substrate and GaN-templated-patterned sapphire substrate (PSS), respectively, as the base substrates for device application, were selectively grown. The surface and the crystal structures of the AlN epilayers were investigated by field emission scanning electron microscopy (FE-SEM) and high-resolution-X-ray diffraction (HR-XRD). From the X-ray photoelectron spectroscopy (XPS) and Raman spectra results, the p-type AlN epilayers grown by using the mixed-source HVPE method could be applied to power devices.

• Journal of Power System Engineering
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• v.4 no.4
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• pp.99-107
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• 2000

In this study several P type and N type ceramic semiconductors were prepared by atomic valence control and their electric resistivities were investigated with various concentrations of additive impurities. N-P junctions were made by thin film printing method and their varistor-like characteristics were investigated and their availability was discussed. The results are followings, 1) Some N type semiconductors with a proper concentration of additive impurity have minimum resistivities. 2) The N-P junction samples with ZnO as a constituent material of N type semiconductor have linearity in voltage-current characteristics, but the other N-P junction samples have the non-linearity, 3) Some N-P junction samples showed the good varistor-like characteristics.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1372-1373
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1927-1934
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• 2016

In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.138-138
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• 2008

Ti capping layer를 이용하여 NiGe의 열적 안정성을 향상시키는 연구를 수행하였다. N-type Ge(100) 기판에 30nm 두께의 Ni과 30nm 두께의 Ti capping layer를 E-beam evaporator를 이용하여 증착하고 $300^{\circ}C$에서 $700^{\circ}C$ 까지 30초간 $N_2$ 분위기에서 급속 열처리하여 Ni-Germanide를 형성하였다. XRD의 결과로부터 Ti capping layer 유무에 상관없이, 전 온도 범위에 걸쳐 NiGe 상이 형성된 것을 관찰할 수 있었다. 급속 열처리 온도에 따른 면저항 값을 측정한 경우, $300^{\circ}C$에서 $600^{\circ}C$까지의 열처리 온도 범위에서는 모든 시편들이 비슷한 면저항 값을 보인 반면, 열처리 온도가 $700^{\circ}C$ 이상에서는 Ti capping layer가 있는 시편이 Ti capping layer가 없는 시편보다 낮은 면저항 값을 갖는 것을 확인할 수 있었다. 이는 고온 열처리 시 Ti capping layer에 있는 Ti가 기판 방향으로 확산하여 NiGe grain boundary에 segregation 되고 그로 인하여 NiGe의 grain boundary 움직임을 억제하여 agglomeration 현상을 효과적으로 방지하였기 때문에 나타난 현상으로 사료된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.10
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• pp.642-647
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• 2014

For feasible study of opto-electrical application regarding to oxide semiconductor, we implemented the N doped ZnO growth using a atomic layer deposition technique. The p-type ZnO deposition, necessary for ZnO-based optoelectronics, has considered to be very difficulty due to sufficiently deep acceptor location and self-compensating process on doping. Various sources of N such as $N_2$, $NH_3$, NO, and $NO_2$ and deposition techniques have been used to fabricate p-type ZnO. Hall measurement showed that p-type ZnO was prepared in condition with low deposition temperature and dopant concentration. From the evaluation of photoluminescence spectroscopy, we could observe defect formation formed by N dopant. In this paper, we exhibited the electrical and optical properties of N-doped ZnO thin films grown by atomic layer deposition with $NH_3OH$ doping source.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.182-186
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• 2005

In this work, thermal evaporation system was employed to deposit thin films of SiC on glass substrates in order to determine the parameters of them. Measurements included transmission, absorption, Seebak effect, resistivity and conductivity, absorption coefficient, type of energy band-gap, extinction coefficient as functions of photon energy and the effect of increasing film thickness on transmittance. Results explained that SiC thin film is an n-type semiconductor of indirect energy band-gap of ${\sim}3eV$, cut-off wavelength of 448nm, absorption coefficient of $3.4395{\times}10^{4}cm^{-1}$ and extinction coefficient of 0.154. The experimental measured values are in good agreement with the typical values of SiC thin films prepared by other advanced deposition techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.152-159
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• 2010

We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.