• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.93-94
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• 2007

다양한 LDD(lightly doped drain)에 따른 n-channel poly-Si TFT (thin film transistor)에 대하여 보고한다. 유리 기판 위에 ELA를 이용하여 만들어진 Polycrystalline silicon (poly-Si)은 TFT-LCD의 응용을 위한 재료로써 우수한 특성을 갖는다. 제작된 n-channel TFT는 절연층으로 $SiN_x$, $SiO_2$의 이중 구조를 갖는다. 다양한 LDD에 따른 n-channel poly-Si TFT의 문턱전압($V_{TH}$), ON/OFF 전류비 ($I_{ON}/I_{OFF}$), 포화전류($I_{DSAT}$)는 TFT의 보다 좋은 성능을 위해 연구된다. 짧은 LLD 길이를 가진 n-channel poly-Si TFT의 문턱전압은 작고, 포화전류의 값은 크다. 또한 긴 LLD 길이를 가진 n-channel poly-Si TFT는 작은 kink effect를 가진다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2002-2007
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• 1999

In this paper, the n-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) on glass were investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. It is done to decide to be applied on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 2, 10, 25$\mu\textrm{m}$ of channel length, the field effect mobilities are 111, 126 and 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus, the poly-Si TFT’s used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate display panel and peripheral circuit on a large glass substrate.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1105-1108
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• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.53-58
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• 1998

A buried channel poly-Si TFT (BCTFT) for application of high performance integrated circuits has been proposed and fabricated. BCTFT has unique features, such as the moderately-doped buried channel and counter-doped body region for conductivity modulation, and the fourth terminal entitled back bias for preventing kink effect. The n-type and p-type BCTFT exhibits superior performance to conventional poly-Si TFT in ON-current and field effect mobility due to moderate doping at the buried channel. The OFF-state leakage current is not increased because the carrier drift is suppressed by the p-n junction depletion between the moderately-doped buried channel and the counter-doped body region.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.718-722
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• 2006

The dependence of n-channel 2 shot SLS poly-Si TFT characteristics on the DOS (density of states) parameters was investigated by using a device simulation. Device performances were most sensitive to the DOS of poly-Si/gate insulator (GI) interface and poly-Si active layer. Deep level states at the poly-Si/GI interfaces strongly affect the subthreshold slope.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.356-356
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• 2010

In this paper, Poly silicon thin-film transistors (poly-Si TFTs) with employed the SPC (Solid phase crystallization) and ELA (Excimer laser annealing) methods on glass panel substrate are fabricated to investigate the electrical poperies. Poly-Si TFTs have recess-channel structure with formated source/drain regions by LPCVD n+ poly Si in low $650^{\circ}C$ temperature. the ELA-TFT show higher on/off current ratio and subthreshold swing than a-Si and SPC TFT that therefore, these results showed that the ELA-TFT might be beneficial for practical embedded TFT memory device application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.91-92
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• 2007

이 논문에서는 다양한 채널길이에 따른 n-채널 다결정 실리콘 TFT의 특징을 보고한다. Excimer laser annealing (ELA)를 이용한 다결정 실리콘은 디스플레이의 재료로써 줄은 특성을 갖는다. 유리기판 위에 buffered oxide 층을 올리고 ELA 처리를 하여 다결정 실리콘을 제작 하였다. 그 위에 $SiO_2$, $SiN_x$를 증착시켜 n-채널 다결정 실리콘 TFT를 만들었다. 다양한 채널의 길이에 따른 n-채널 TFT의 문턱전압 ($V_{TH}$), ON/OFF 전류비($I_{ON}/I_{OFF}$), 포화 전륙(IDSAT)를 조사하였다. 그 결과 채널의 길이가 짧은 소자에서 더 줄은 TFT의 특징이 나타난다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.7
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1615-1622
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• 2008

We have fabricated the poly-silicon thin film transistor(TFT) which has the LDD-region with graded spacer. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $H_2$/plasma processes were fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring/analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplicities of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.101-105
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• 2000

The effects of electrical on n-channel offset gated poly-Si TFT's have been investigated. It is observed that the electrical field near the drain region in offset devices is smaller than that of conventional device by simulation results. The variation rate of threshold voltage and subthreshold slope decrease with increasing the offset length because of lowering the electric field near the drain region. The offset gated poly-Si TFT's have been probed effective in reducing the degradation rate of device performance under electrical stressing.