• The Journal of Engineering Research
• /
• v.2 no.1
• /
• pp.73-82
• /
• 1997

In this paper, we examine design trends in the development of distributed real-time system. Many real-time systems developed over the last ten years share common characteristics including use of communications, imprecise computations, the object-oriented paradigm, multiprocessor node hardware, dynamic time-driven scheduling and the inclusion of fault tolerance mechanisms. By examining the major design decisions made in previous systems, the best attributes of these systems can be coalesced together to form the "ideal" real-time system. This paper examines such a system and the advantages and disadvantages of the design decisions involved.

• ETRI Journal
• /
• v.43 no.3
• /
• pp.471-482
• /
• 2021

Several code-division multiple access (CDMA)-based interconnect schemes have been recently proposed as alternatives to the conventional time-division multiplexing bus in multicore systems-on-chip. CDMA systems with a dynamic assignment of spreading codewords are particularly attractive because of their potential for higher bandwidth efficiency compared with the systems in which the codewords are statically assigned to processing elements. In this paper, we propose a novel distributed arbitration scheme for dynamic CDMA-bus-based systems, which solves the complexity and scalability issues associated with commonly used centralized arbitration schemes. The proposed arbitration unit is decomposed into multiple simple arbitration elements, which are connected in a ring. The arbitration ring implements a token-passing algorithm, which both resolves destination conflicts and assigns the codewords to processing elements. Simulation results show that the throughput reduction in an optimally configured dynamic CDMA bus due to arbitration-related overheads does not exceed 5%.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.421-425
• /
• 1999

As the market size of multiprocessor systems for commercial applications, parallel systems, especially cache-coherent shared-memory multiprocessors that are conventionally designed for scientific applications need to be tuned in different fashion to achieve the best performance for new application area. In this paper, indepth investigation on the memory behavior which is the primary cause for performance changes were made. We chose representative benchmarks in scientific and commercial application areas. After running execution-driven simulation for bus-based cache-coherent shared-memory multiprocessors, we experienced significant differences and conclude that the systems must be carefully and differently designed to achieve the best performance when they are built for distinct applications.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.8B
• /
• pp.701-706
• /
• 2006

System-level diagnosis plays an important technique for fault detection in multi-processor systems. Efficient diagnosis is very important for real time systems as well as multiprocessor systems. Feng(1) proposed two adaptive diagnosis algorithms HADA and IHADA for hypercube system. The diagnosis cost, measured by diagnosis time and the number of test links, depends on the number and location of the faults. In this paper, we propose an adaptive diagnosis algorithm using the syndrome analysis. This removes unnecessary overhead generated in HADA and IHADA algorithm sand give a better performance compared to Feng's Method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.22-28
• /
• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.6
• /
• pp.1502-1510
• /
• 1999

In adaptive job allocation method for multiprocessor systems a job is folded, or split in two halves, to fit for an available subcube in order to reduce the waiting time of jobs. In this method, however, since a job is folded whenever a subcube with the proper size is not found, the prolonged execution time caused by job split may override the savings in waiting time, in which case the total adaptive jobs may be increased. In this paper, an improved adaptive job allocation algorithm, called Estimate-fold allocation, Is presented and evaluated. The proposed algorithm estimates the costs and takes the better of two alternatives ; folding right away and waiting until a bigger subcube becomes available. The average total job execution cost of our algorithm is calculated and compared to those of the conventional adaptive, buddy, and gray-code algorithms through simulations. The results shows that our proposed algorithm performs better than others.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.5
• /
• pp.196-208
• /
• 2005

In multiprocessor systems, interconnection network design is critical for overall system performance. Popular interconnection networks, which are generally considered, are meshes, rings, and hierarchical rings. In this paper, we propose (')Torus Ring('), which is a modified version of hierarchical ring. Torus Ring has the same complexity as the hierarchical rings, but the only difference is the way it connects the local rings. It has an advantage over the hierarchical rings when the destination of a packet is the neighbor local ring in the reverse direction. Though the average number of hops in Torus Ring is equal to that of the hierarchical rings when assuming the uniform distribution of each transaction, the benefits of the number of hops are expected to be larger because of the spatial locality in the real environment of parallel programming. In the simulation results, latencies in the interconnection network are reduced by up to 19$\%$, and the execution times are reduced by up to 10$\%$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.12 no.2
• /
• pp.62-68
• /
• 1998

In this paper, we proposed the design of the intelligent traffic control system by using multiprocessor architecture. The inter-processor communication of the architecture is implemented by sharing the serial communication channel. In comparing the conventional traffic control system using single processor architecture, the proposed system uses multiple processors controlling the sub systems such as the signal lights, traffic measurement unit, auxiliary signal lights and peripherals. The main processor controls the communication among the processors and the communication protocol link to the central control center at remote site. The proposed architecture reduces the load and simplifies the program of each processor and enables the real time processing of the add-on features of intelligent traffic control systems. The architecture is implemented and the common channel inter-processor communications and the real time operation is experimented .experimented .

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.2
• /
• pp.177-187
• /
• 2000

In the past several years, many systems which adopted ring topology with high-speed unidirectional point-to-point links have emerged to overcome the limit of bus for interconnection network of clustered multiprocessor system. However, rapid increase of processor speed and performance improvement of local bus and memory system limit scalability of system with point-to-point link of standard bandwidth. Therefore, necessity to extend bandwidth is emphasized. In this paper, we adopt PANDA system as base model, which is clustering-based multiprocessor system. By simulating a model adopting commercial processor and local bus specification, we show that point-to-point link is bottleneck of system performance, and bandwidth expansion by more than 200% is needed. To expand bandwidth of interconnection network, it needs excessive design cost and time to develop new point-to-point link with doubled bandwidth. As an alternative to double bandwidth, we propose several ways to implement dual ring -simple dual ring, transaction-separated dual ring, direction-separated dual ring- by using off-the-shelf point-to-point links with IEEE standard bandwidth. We analyze pros. and cons. of each model compared with doubled-bandwidth single ring by simulation.

• Proceedings of the KIEE Conference
• /
• 1992.07a
• /
• pp.365-368
• /
• 1992

This paper presents an approach to the design of real time task scheduling for a line controller of continuous manufacturing process automation. The line controller has multiprocessor-based architecture with shared memory and is operated by firmware. This firmware contains menu-driven software supporting real-time database management and fuction-block control language. The multitasking line control processor performs the following three functions: 1) interprets the function block control language by virtue of shared memory in the database; 2) invokes an interupt service routine as required by external hardware; 3) detects errors and notifies the user. We propose real time task scheduling method.