• Journal of Elementary Mathematics Education in Korea
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• v.20 no.3
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• pp.407-430
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• 2016

In this study, we analyzed and discussed the instruction method of multiplication tables in mathematics textbooks from four countries in Asia; South Korea, China, Japan, and Singapore. The conclusions of remarks are states as follows: First. The teaching period and elements should be subdivided more structurally so that the learner could understand the concept and principle of multiplication tables better. Second. The bundle model, the linear model, and the array model of multiplication need to be presented so that the learners could experience various situations related to multiplication. Third, The concrete explanation and the higher frequency of presenting the commutative rules of multiplication is suggested so that the learner could understand the concept of the rules well. Fourth. The context related to multiplication by 1 and 0 should be presented so that the learner could comprehend the character of multiplication by 1 and 0. Fifth. The activities which helping memorizing a multiplication table should be suggested when the memorization is needed.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.7
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• pp.2610-2630
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• 2021

The aim of this paper is to propose the alternative algorithm to finish the process in public key cryptography. In general, the proposed method can be selected to finish both of modular exponentiation and point multiplication. Although this method is not the best method in all cases, it may be the most efficient method when the condition responds well to this approach. Assuming that the binary system of the exponent or the multiplier is considered and it is divided into groups, the binary system is in excellent condition when the number of groups is small. Each group is generated from a number of 0 that is adjacent to each other. The main idea behind the proposed method is to convert the exponent or the multiplier as the subtraction between two integers. For these integers, it is impossible that the bit which is equal to 1 will be assigned in the same position. The experiment is split into two sections. The first section is an experiment to examine the modular exponentiation. The results demonstrate that the cost of completing the modular multiplication is decreased if the number of groups is very small. In tables 7 - 9, four modular multiplications are required when there is one group, although number of bits which are equal to 0 in each table is different. The second component is the experiment to examine the point multiplication process in Elliptic Curves Cryptography. The findings demonstrate that if the number of groups is small, the costs to compute point additions are low. In tables 10 - 12, assigning one group is appeared, number of point addition is one when the multiplier of a point is an even number. However, three-point additions are required when the multiplier is an odd number. As a result, the proposed method is an alternative way that should be used when the number of groups is minimal in order to save the costs.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.277-280
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• 2000

In this paper, we designed a turbo decoder using VHDL. To maximize effective free distance of the turbo code, we implemented pseudo random interleaver. A MAP(Maximum a posteriori) decoder is used as a primimary decoder. We avoided multiplication by using lookup tables(ROM). We expect that this small-sized turbo decoder is suitable for mobile communication. We simulated turbo decoder with Altera MAX+PLUS II.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.5
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• pp.285-292
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• 2014

The commonly used Newton-Raphson's floating-point number divider algorithm performs two multiplications in one iteration. In this paper, a tentative K'th Newton-Raphson's floating-point number divider algorithm which performs K times multiplications in one iteration is proposed. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation in single precision and double precision divider is derived from many reciprocal tables with varying sizes. In addition, an error correction algorithm, which consists of one multiplication and a decision, to get exact result in divider is proposed. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a floating point number divider unit. Also, it can be used to construct optimized approximate reciprocal tables.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.5
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• pp.1036-1044
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• 1997

We modify the montgomery modeular multikplication to extract the common parts in common-multiplicand multi-plications. Since the modified method computes the common parts in two modular multiplications once rather than twice, it can speed up the exponentiations and reduce the amount of storage tables in m-ary or windowexponentiation. It can be also applied to an exponentiation mehod by folding the exponent in half. This method is well-suited to the memory limited environments such as IC card due to its speed and requirement of small memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1786-1792
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• 2015

Random linear network coding (RLNC) is widely employed to enhance the reliability of wireless multicast. In RLNC encoding/decoding, Galois Filed (GF) arithmetic is typically used since all the operations can be performed with symbols of finite bits. Considering the architecture of commercial computers, the complexity of arithmetic operations is constant regardless of the dimension of GF m, if m is smaller than 32 and pre-calculated tables are used for multiplication/division. Based on this, we show that the complexity of RLNC inversely proportional to m. Considering additional overheads, i.e., the increase of header length and memory usage, we determine the practical value of m. We implement RLNC in a commercial computer and evaluate the codec throughput with respect to the type of the tables for multiplication/division and the number of original packets to encode with each other.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.6
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• pp.95-109
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• 2006

Elliptic Curve Cryptosystem (ECC) is suitable for resource-constrained devices such as smartcards, and sensor motes because of its short key size. This paper presents an efficient multi-scalar multiplication algorithm which is the main component of the verification procedure in Elliptic Curve Digital Signature Algorithm (ECDSA). The proposed algorithm can make use of a precomputed table of variable size and provides an optimal efficiency for that precomputed table. Furthermore, the given scalar is receded on-the-fly so that it can be merged with the main multiplication procedure. This can achieve more savings on memory than other receding algorithms. Through experiments, we have found that the optimal sizes of precomputed tables are 7 and 15 when uP+vQ is computed for u, v of 163 bits and 233 bits integers. This is shown by comparing the computation time taken by the proposed algorithm and other existing algorithms.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.2
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• pp.179-187
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• 2020

The FBC(Fixed-Base Comb) is a method to efficiently operate scalar multiplication, a core operation for signature generations of the ECDSA(Elliptic Curve Digital Signature Algorithm), utilizing precomputed lookup tables. Since the FBC refers to the table depending on the secret information and the values of the table are publicly known, an adversary can perform HCA(Horizontal Correlation Analysis), one of the single trace side channel attacks, to reveal the secret. However, HCA is a statistical analysis that requires a sufficient number of unit operation traces extracted from one scalar multiplication trace for a successful attack. In the case of the scalar multiplication for signature generations of ECDSA, the number of unit operation traces available for HCA is significantly fewer than the case of the RSA exponentiation, possibly resulting in an unsuccessful attack. In this paper, we propose an improved HCA on lookup table based scalar multiplication algorithms such as FBC. The proposed attack improves HCA by increasing the number of unit operation traces by determining such traces for the same intermediate value through collision analysis. The performance of the proposed attack increases as more secure elliptic curve parameters are used.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1216-1224
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• 1988

In this paper, it is presented element generation, addition, multiplication and division algorithm over GF ($2^m$) to calculate multiple-valued logic function. The results of addition and multiplication among these algorithms are applied to the current mode CMOS circuits with ROM structure to design of adder and multiplier on GF ($2^m$). Table-lookup and Euclid's algorithm are required the computation in large quentities when multiple-valued logic functions are developed on GF ($2^m$). On the contrary the presented operation algorithms are prefered to the conventional methods since they are processed without relation to increasing degree m in the general purpose computer. Also, the presened logic circuits are suited for the circuit design of the symmetric multiplevalued truth-tables and they can be implemented addition and multiplication on GF ($2^m$) simultaueously.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.278-281
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• 1988

This paper realizes the multi-output truncated difference circuits using current mode CMOS, and presents the algorithm designing multi - valued logic functions of a given multivalued truth tables. This algorithm divides the discrete valued functions and the interval functions, and transforms them into the truncated difference functions. The transformed functions are realized by current mode CMOS. The technique presented here is applied to MOD4 addition circuit and GF(4) multiplication circuit.