• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.22-28
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• 2015

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.22 no.2
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• pp.273-282
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• 1992

The purpose of this study was to propose the utility which was evaluated the digital image processing and clinical application of the videodensitomery. The experiments were performed with IBM-PC/16bit-AT compatible, video camera(CCdtr55, Sony Co., Japan), an color monitor(MultiSync 3D, NEC, Japan) providing the resolution of 512×480 and 64 levels of gray. Sylvia Image Capture Board for the ADC(analog to digital converter) was used, composed of digitized image from digital signal and the radiographic density was measured by 256 level of gray. The periapical radiograph(Ektaspeed EP-21, Kodak Co., U. S. A) which was radiographed dried human mandible by exposure condition of 70 kVp and 48 impulses, was used for primary X-ray detector. And them evaluated for digitzed image by low and high pass filtering, correlations between aluminum equivalent values and the thickness of aluminum step wedge, aluminum equivalent values of sound enamel, dentin, and alveolar bone, the range of diffuse density for gray level ranging from 0 to 255. The obtained results were as follows: 1. The edge between aluminum steps of digitized image were somewhat blurred by low pass filtering, but edge enhancement could be resulted by high pass filtering. Expecially, edge enhancement between distal root of lower left 2nd molar and alveolar lamina dura was observed. 2. The correlation between aluminum equivalent values and the thickness of aluminum step wedge was intimated, yielding the coefficient of correlation r=0.9997(p<0.00l), the regression line was described by Y=0.9699X+0.456, and coefficient of variation amounting to 1.5%. 3. The aluminum equivalent values of sound enamel, dentin, and alvolar bone were 15.41㎜, 12.48㎜, 10.35㎜, respectively. 4. The range of diffuse density for gray level ranging from 0 to 255 was wider enough than that of photodenstiometer to be within the range of 1-4.9.