• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.105-112
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• 1997

The performance of a shared memory multiprocessor system is very sensitive to process scheduling. w can enhance the performance of a whole system as well as of an individual process by taking the multiprocessor characteristics into account in the design of the process scheduler. In this paper, we proposed a general purpose scheduler for a shared memory multiprocessor, called the Two-Level Multi-Scan (TLMS) process scheduler, that considers the processor affinity loosely and decreases the interference among multiple processors greatly. The TLMS scheduler is composed of a local scheduler at each processor and a semi-global scheduler that balances the load among processors. In particular, the semi-global scheduler tries to minimize priority inversion, which is an important factor of the system performance. The TLMS scheduler also tries to reduce the number of resources to be shared and improves the processor utilization. to meet these requirements, th semi-global scheduler interacts with the operation of the local scheduler when a need arises, thus the name is loose processor-affinity. We also show that the proposed scheduling technique can be extended for other types of resources making it a general purpose resource management queue.

• Management Science and Financial Engineering
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• v.11 no.1
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• pp.63-78
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• 2005

Disassembly scheduling is the problem of determining the ordering and disassembly schedules of used or end-of-life products while satisfying the demand of their parts or components over a certain planning horizon. This paper considers the case of the assembly product structure for the cost-based objective of minimizing the sum of purchase, setup, inventory holding, and disassembly operation costs. To represent and solve the problem optimally, this paper presents an integer programming model, which is a reversed form of the multi-level lot sizing formulation. Computational experiments on an example derived from the literature and a number of randomly generated test problems are done and the results are reported.

• Journal of KIISE
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• v.44 no.2
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• pp.115-123
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• 2017

A message processor is server software that receives non-realtime messages as well as realtime messages from clients that need to be processed within a deadline. With the recent advances of micro-processor technologies and Linux, the message processor is often implemented in Linux-based multi-core servers and it is important to use cores efficiently to maximize the performance of system in multi-core environments. Numerous research efforts on a real-time scheduler for the efficient utilization of the multi-core environments have been conducted. Typically, though, they have been conducted theoretically or via simulation, making a subsequent real-system application difficult. Moreover, many Linux-based real-time schedulers can only be used in a specific Linux version, or the Linux source code needs to be modified. This paper presents the design of a Linux-based message processor for multi-core environments that maps the threads to the cores at user level. The message processor is implemented through a modification of the traditional RM algorithm that consolidates the real-time messages into certain cores using a first-fit-based bin-packing algorithm; this minimizes the response-time delay of the non-real-time messages, while guaranteeing the violation rate of the real-time messages. To compare the performances, the message processor was implemented using the two multi-core-scheduling algorithms GSN-EDF and P-FP, which are provided by the LITMUS framework. The benchmarking results show that the response-time delay of non-real-time messages in the proposed system was improved up to a maximum of 17% to 18%.

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.6
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• pp.69-75
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• 2022

We propose energy-efficient scheduling considering real-time constraints and energy efficiency in smart mobile with heterogeneous multi-core structure. Recently, high-performance applications such as VR, AR, and 3D game require real-time and high-level processings. The big.LITTLE architecture is applied to smart mobiles devices for high performance and high energy efficiency. However, there is a problem that the energy saving effect is reduced because LITTLE cores are not properly utilized. This paper proposes a heterogeneous multi-core assignment technique that improves real-time performance and high energy efficiency with big.LITTLE architecture. Our proposed method optimizes the energy consumption and the execution time by predicting the actual task execution time using SVM (Support Vector Machine). Experiments on an off-the-shelf smartphone show that the proposed method reduces energy consumption while ensuring the similar execution time to legacy schemes.

• Journal of Korean Institute of Industrial Engineers
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• v.26 no.1
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• pp.17-26
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• 2000

This paper presents an integrated order scheduling method with the improved DRP concept for multi-echelon distribution system that has the constraint of limited production capacity of producers. The proposed method reflects the dynamic characteristics of inventory level changes in the regional and central distribution center. The simulation is done with two models : the traditional DRP method and the proposed method presented in this paper. From the results, the latter is more efficient than the former in cost, customer's service level as well as balanced production load on each producer.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.3
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• pp.1091-1110
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• 2016

Hybrid deployment under current cloud data centers is a combination of online and offline services, which improves the utilization of the cluster resources. However, the performance of the cluster is often affected by the online services in the hybrid deployment environment. To improve the response time of online service (e.g. search engine), an effective scheduling algorithm based on Storm is proposed. At the component level, the algorithm dispatches the component with more influence to the optimal performance node. Inside the component, a reasonable resource allocation strategy is used. By searching the compressed index first and then filtering the complete index, the execution speed of the component is improved with similar accuracy. Experiments show that our algorithm can guarantee search accuracy of 95.94%, while increasing the response speed by 68.03%.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.832-834
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• 2005

임베디드 시스템은 범용 컴퓨팅 시스템과 달리 자신을 포함하고 있는 기기에 부과된 특정 목적의 컴퓨팅 작업만을 수행한다. 이 시스템을 제어하기 위해서 운영체제가 필요로 하며, 임베디드 환경에서는 신뢰성과 정확성을 요하는 부분이 많기 때문에 실시간 운영체제를 필요로 한다. Real-Time kernel을 기반으로 하는 MicroC/OS-II는 수많은 용도로 사용되고 있지만 task 사용에 한계가 있다. 이 논문에서 제안하는 스케줄링은 task의 생성 수를 늘려주지만, 이 경우 task간의 우선순위 설정이 어려워진다. 이 문제 해결을 위해서 task들의 우선순위 결정은 deadline을 이용하여 3레벨로 나눈다. 3레벨로 나누어지면 task의 수가 증가해도 개발자는 task들을 레벨에 맞게 설정하면 task 관리로 인하여 생기는 문제를 줄일 수 있으며, 효율적인 스케줄링을 가능하게 한다.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.12 no.19
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• pp.39-47
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• 1989

This paper considers a multi-stage flowshop scheduling Problem where the setup times of jots depend on immediately preceding jobs. Three heuristics algorithms, CAMPBELL, PEIDAN and CAMRING are proposed. The performance measure is a minimization of makespan. The parameters of simulation model are PS(ratio of the processing times to setup times), M(number of machines), and N(number of job). This simulation model for each algorithm is a 4$\times$3$\times$3 factorial design with 360 observations. The makespan of the proposed heuristic algorithms is compared with the optimal makespan obtained by the complete enumeration of schedules. This yardstick of comparison is defined as a relative error. The mean relative error of CAMPBELL, PEIDAN, and CAMRING algorithms are 4.353%, 7.908%, and 8.578% respectively. The SPSS, is used to analyse emphirical results. The experimental results show that the three factors are statistically significant at 5% level.

• International Journal of Precision Engineering and Manufacturing
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• v.1 no.2
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• pp.124-131
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• 2000

A shop floor can be considered as and importand level to develop a Computer Integrated Manufacturing system (CIMs). The shop foor is a dynamic environment where unexpected events contrinuously occur, and impose changes to planned activities. The shop floor should adopt an appropriate control system that is responsible for scheduling coordination and moving the manufacturing material and information flow. In this paper, the architecture of the hybrid control model identifies three levels; i.e., the shop floor controller (SFC), the cell controller(CC) and the equipment controller (EC). The methodology for developing these controller is employ an object-oriented approach for static models and IDEF0 for function models for dispatching a job. SFC and CC are coordinated by employing a multi-factors bidding and an adapted Analytic Hierarchy Process(AHP) prove applicability of the suggested method. Test experiment has been conducted by with the shopfloor, consisting of six manufacturing cells.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.76-78
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• 2002

최근 멀티미디어 데이터 서버로 리눅스 시스템을 쓰는 경우가 많아 졌다. 이 경우, 멀티미디어 데이터에 관한 서비스를 효율적으로 제공할 수 있어야 한다. 이를 위하여, 본 논문에서는 기존의 리눅스 scheduling 방식이 갖는 단일레벨 run-queue 구조를 변형한 다중레벨 run-queue를 제안하였다. 기존의 단일레벨 run-queue에서는 queue 내에 프로세스의 수가 많아질수록 검색시간이 길어지는 단점이 있다. 본 논문에서는 기존의 run-queue를 여러 단계로 나누고, scheduling 과정에서 상위 queue부터 프로세스가 존재하는지를 조사하도록 스케줄러를 변형하였다. 따라서, 상위 queue에 프로세스가 있는 경우에는 하위의 queue는 더 이상 조사한 필요가 없게 되므로. 결과적으로 검색시간을 줄일 수 있게 된다. 한편, 다중 레벨의 run-queue를 사용할 경우, 이를 관리하기 위한 오버헤드가 별도로 발생한다. 본 논문에서는, 제안한 다중레벨의 run-queue 시스템의 성능을 최적화하기 위하여, queue의 적절한 개수 선정 및 각 프로세스를 어떤 queue에 넣을 것인지를 결정하는 것이 성능에 미치는 영향에 대하여 실험적으로 연구하여 새로운 스케줄러의 성능을 기존 스케줄러와 비로 분석하였다. 본 논문에서 제안한 멀티레벨 run-queue를 사용함으로써, 각 queue의 스케줄링 정책(policy)과 관련 파라메터 간을 독자적으로 변화시킬 수 있다. 따라서, 여러 가지 상황에 적합한 스케줄링을 각각의 경우에 맞게 최적화하는 것이 손쉬워 지므로 여러 분야에서 매우 유용하게 쓰일 것이다.