• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.865-868
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• 2001

TCM offers considerable coding gains without compromising bandwidth or signal power. But TCM decoder is more complex than convolutional Viterbi decoder. Because, the number of branches exponentially increased by the constraint length and input symbol bits. The parallelism of ACS and memory management technique of SPMM is one of the important factor for speed-up and hardware complexity. This paper proposes a multi-processing technique of ACS and also gives a memory management technique of SPMM in TCM decoders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.4
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• pp.180-187
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• 2014

In this paper, a extension of a fixed-complexity sphere decoder (FSD) to perform interference signal detection and cancelling is proposed for downlink multiuser multiple input-multiple output (MIMO) communication system. It is based on the application of channel matrix expansion on generalized sphere decoder (GSD), and modification of the channel matrix ordering scheme to a FSD algorithm for interference detection. A Monte Carlo simulation shows that the proposed algorithm improves the receiver performance by 3 dB as compared to maximum likelihood detection without interference cancelling at 10% packet error rate in configuration of 702 Mbit/s datarate for four users respectively on IEEE802.11ac.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• Journal of Communications and Networks
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• v.6 no.3
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• pp.203-208
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• 2004

A combined precoding and turbo decoding strategy for multi-path frequency-selective fading channels is presented. The precoder and multi-path fading channel are jointly modeled as a finite-state probabilistic channel to provide the multi-stage turbo decoder with its statistics information. Both a priori and a posteriori probabilities are used in the metric computation to improve the system performance. Structures of the combined turbo-encoder, interleaver, and precoder in the transmitter and two-stage turbo decoder in the receiver are described. Performance of the proposed scheme in fixed, Rician and Rayleigh multi-path fading channels are evaluated by simulation. The results indicate that the combined precoding and two-stage turbo decoding strategy provides a considerable performance improvement while maintaining the same inner structure of a conventional turbo decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5A
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• pp.359-369
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• 2005

For large capacity optical CDMA networks, we propose a shared-type encoder/decoders based on an tunable wavelength converter(TWC) and an arrayed waveguide grating (AWG) router. The proposed encoder/decoder treats codewords of wavelength/time 2-D code simultaneously using the dynamic code allocation property of the TWC and the cyclic property of the AWG router, and multiple subscribers can share the encoder/decoder in networks. Feasibility of the structure of the proposed encoder/decoder for dynamic code allocation is tested through simulations using two wavelength/time 2-D codes, which are the generalized multi-wavelength prime code(GMWPC) and the generalized multi-wavelength Reed-Solomon code(GMWRSC). Test results show that the proposed encoder/decoder can increase the channel efficiency not only by increasing the number of simultaneous users without any multiple-access interference but by using a relatively short length CDMA codes.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.350-353
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• 2007

This paper presents an real-time implementation of H.264/AVC High 4:4:4 Predictive profile decoder using general-purpose processors by exploiting multi-threading technique and Single Instruction Multiple Data (SIMD) instructions without any quality degradation. We analyze differences between the existing High profile and High 4:4:4 Predictive profile decoder, and show various optimization techniques to decode high fidelity and high definition (HD) video in real-time. Simulation results show that the proposed decoder can play high fidelity HD video at average 40 frames per seconds (fps) for the IBBrBP bistream and about 50 fps for the Intra-only bitstream.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2013-2014
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• 2006

For large capacity optical CDMA networks, we propose a shared-type encoder/decoder based on an tunable wavelength conveter (TWC) and an arrayed waveguide grating (AWG) router. Feasibility of the structure of the proposed encoder/decoder for dynamic code allocation is tested through simulations using three types of wavelength/time 2-D codes, which are the generalized multi-wavelength prime code(GMWPC), the generalized multi-wavelength Reed-Solomon code(GMWRSC) and the matrix code. Test results show that the proposed encoder/decoder can increase the channel efficiency not only by increasing the number of simultaneous users without any multiple-access interference but by using a relatively short length CDMA codes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.