• Proceedings of the IEEK Conference
• /
• 2004.06a
• /
• pp.47-50
• /
• 2004

In this paper, we implement an Elliptic Curve Cryptosystem(ECC) processor for DTCP. Because DTCP(Digital Transmission Content Protection) uses GF(p), where p is a 160-bit prime integer, we design a scalar multiplier based on GF(p). The scalar multiplier consists of a modular multiplier and an adder. The multiplier uses montgomery algorithm which is implemented with CSA(Carry-save Adder) and CLA(Carry-lookahead Adder). Our new scalar multiplier has been synthesized using Samsung 0.18 um CMOS technology and the maximum operation frequency is estimated 98 MHz, with the size about 65,000 gates. The resulting performance is 29.6 kbps, that is, it takes 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• ETRI Journal
• /
• v.30 no.6
• /
• pp.818-825
• /
• 2008

This paper proposes an exponentiation method with Frobenius mappings. The main target is an exponentiation in an extension field. This idea can be applied for scalar multiplication of a rational point of an elliptic curve defined over an extension field. The proposed method is closely related to so-called interleaving exponentiation. Unlike interleaving exponentiation methods, it can carry out several exponentiations of the same base at once. This happens in some pairing-based applications. The efficiency of using Frobenius mappings for exponentiation in an extension field was well demonstrated by Avanzi and Mihailescu. Their exponentiation method efficiently decreases the number of multiplications by inversely using many Frobenius mappings. Compared to their method, although the number of multiplications needed for the proposed method increases about 20%, the number of Frobenius mappings becomes small. The proposed method is efficient for cases in which Frobenius mapping cannot be carried out quickly.

• Journal of information and communication convergence engineering
• /
• v.7 no.2
• /
• pp.107-112
• /
• 2009

Renewable energy resources will be an increasingly important part of power generation in the new millennium. Besides assisting in the reduction of the emission of greenhouse gases, they add the much needed flexibility to the energy resource mix by decreasing the dependence on fossil fuels. Due to their modular characteristics, ease of installation and because they can be located closer to the user, PV system have great potential as distributed power source to the utilities. In this paper, a dc-de power converter scheme with the push-pull based technology is proposed to apply for solar power system which has many features such as high efficiency, stable output, and low acoustic noises, DC-DC converter is used in proposed topology has stable efficiency curve at all load range and very high efficiency characteristics. This paper presents the design of a single-phase photovoltaic inverter model and the simulation of its performance.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.26 no.6
• /
• pp.397-403
• /
• 2021

In this paper, phase shedding algorithm that measuring to converter's input and output parameter during real-time to control the number of driving converters is proposed. The proposed phase-shedding algorithm drives the DVR power supply with the optimal converter's combination without the loss calculation curve and the lookup table in which the efficiency is measured in advance. The proposed algorithm was implemented through a digital controller and verified in a two-modular LLC converter with a single rated power of 60 Win a 120 W DVR power supply system. Experimental results are presented to prove the validity of the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.7
• /
• pp.1071-1077
• /
• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• KSCE Journal of Civil and Environmental Engineering Research
• /
• v.34 no.1
• /
• pp.73-85
• /
• 2014

The CFT (Concrete Filled steel Tubes) column-footing connection is cast-in-place embedded type which provides simple construction procedure, low cost, and superior structural performance. In this study, CFT column-footing connection of modular pier is proposed and structural performance is evaluated by experimental tests. To evaluate structural performance of the CFT column-footing connection, a series of experimental tests were performed for the 4 specimens with different embedded depth. As a result of the quasi-static test, the specimen with 0.6D (0.6 times the outside diameter of steel tube) embedded depth showed relatively low ductility than other specimens with larger embedded depth due to cone failure of base concrete occurred during the lower loading step. On the contrary, cone failure of the base concrete was not observed in the specimens with larger embedded depth than 0.9D, but typical flexural failure in lower part of CFT column was observed. With the analyses of force-displacement curve, displacement ductility, and energy dissipation capacity, it is concluded that the rational range of embedded depth of the CFT column-footing connection is from 0.9D to 1.2D in view of good seismic performance.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.6 s.336
• /
• pp.67-74
• /
• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.49-54
• /
• 2008

In cryptosystems based on finite fields, a modular multiplication operation is the most crucial part of finite field arithmetic. Also, in multipliers with resource constrained environments, bit-serial output structures are used in general. This paper proposes two efficient bit-serial output multipliers with the polynomial basis representation for irreducible trinomials. The proposed multipliers have lower time complexity compared to previous bit-serial output multipliers. One of two proposed multipliers requires the time delay of $(m+1){\cdot}MUL+(m+1){\cdot}ADD$ which is more efficient than so-called Interleaved Multiplier with the time delay of $m{\cdot}MUL+2m{\cdot}ADD$. Therefore, in elliptic curve cryptosystems and pairing based cryptosystems with small characteristics, the proposed multipliers can result in faster overall computation. For example, if the characteristic of the finite fields used in cryprosystems is small then the proposed multipliers are approximately two times faster than previous ones.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.5
• /
• pp.1471-1481
• /
• 2014

This paper presents the new power dissipation model of individual switching device in a high-level modular multilevel converter (MMC), which can be mostly used in voltage sourced converter (VSC) based high-voltage direct current (HVDC) system and flexible AC transmission system (FACTS). Also, the voltage balancing method based on sorting algorithm is newly proposed to advance the MMC functionalities by effectively adjusting switching variations of the sub-module (SM). The proposed power dissipation model does not fully calculate the average power dissipation for numerous switching devices in an arm module. Instead, it estimates the power dissipation of every switching element based on the inherent operational principle of SM in MMC. In other words, the power dissipation is computed in every single switching event by using the polynomial curve fitting model with minimum computational efforts and high accuracy, which are required to manage the large number of SMs. After estimating the value of power dissipation, the thermal condition of every switching element is considered in the case of external disturbance. Then, the arm modeling for high-level MMC and its control scheme is implemented with the electromagnetic transient simulation program. Finally, the case study for applying to the MMC based HVDC system is carried out to select the appropriate insulated-gate bipolar transistor (IGBT) module in a steady-state, as well as to estimate the proper thermal condition of every switching element in a transient state.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.5
• /
• pp.2680-2700
• /
• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.