• Korean Journal of Optics and Photonics
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• v.11 no.6
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• pp.411-417
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• 2000

The waveguide structure effects of a spot-size converter (SSe) of a $1.3\mu{m}$ FP(Fabry-Perot)-LD(Laser Diode) were investigated. Its coupling efficiency and alignment tolerance with a single-mode fiber (SMF) were carefully examined by using a 3dimensional BPM (Beam Propagation Method). It was shown that the fOlmation of enough length of straightened waveguide around the end of the sse region can substantially improve the optical coupling efficiency for a vertically tapered sse. In contrast, a down-taper structure for a laterally tapered sse has superior characteristics to an up-tapered one. We suggested good sse structures which can provide a high coupling efficiency as well as a large alignment tolerance with an .SMF. .SMF.

• ETRI Journal
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• v.27 no.1
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• pp.89-94
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• 2005

This paper describes a low-loss, compact, 40-channel arrayed waveguide grating (AWG) which utilizes a monolithically integrated spot-size converter (SSC) for lowering the coupling loss between silica waveguides and standard single-mode fibers. The SSC is a simple waveguide structure that is tapered in both the vertical and horizontal directions. The vertically tapered structure was realized using a shadow-mask etching technique. By employing this technique, the fabricated, 40-channel, 100 GHz-spaced AWG with silica waveguides of 1.5% relative index-contrast showed an insertion-loss figure of 2.8 dB without degrading other optical performance.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.47-54
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• 2020

Integration of active and passive waveguides is an essential component of the photonic integrated circuit and its elements. Butt joint is one of the important technologies to accomplish it with significant advantages. However, it suffers from high optical loss at the butt joint junction and need of accurate process control to align both waveguides. In this study, we used beam propagation method to simulate an integrated device composed of a laser diode and spot size converter (SSC). Two SSCs with different mode properties were combined with laser waveguide and optical coupling efficiency was simulated. The SSC with larger near field mode showed lower coupling efficiency, however its far field pattern was narrower and more symmetric. Tapered passive waveguide was utilized for enhancing the coupling efficiency and tolerance of waveguide offset at the butt joint without degrading the far field pattern. With this technique, high optical coupling efficiency of 89.6% with narrow far field divergence angle of 16°×16° was obtained.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.435-437
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• 2007

Authors propose a PFC(power factor correction) Buck-Boost AC-DC converter by soft switching method. The proposed converter for a discontinuous conduction mode eliminates the complicated control requirement and reduces the size of components. The input current waveform in the converter is got to be a sinusoidal form of discontinuous pulse in proportion to magnitude of ac input voltage under the constant duty cycle switching.Therefore,the input power factor is nearly unity and the control algorithm is simple. To achieve high efficiency system, the proposed converter is constructed by using a partial resonant technique. The control switches using in the converter are operated with soft switching for a partial resonant. The control switches are operated without increasing their voltage and current stresses by the soft switching method. The result is that the switching loss is very low and the efficiency of converter is high.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.53-58
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• 2021

Operation of the interleaved Boost PFC converter in Critical Conduction Mode (CrM) shows the advantages of high efficiency and good EMI characteristics owing to the valley switching of FET. However, when it is designed for a highly pulsating load, operation at a relatively high frequency is inevitable at non-pulsating typical load condition, resulting in efficiency degradation. Moreover, the physical size of the inductor becomes problematic because of the nature of the CrM operation, where the inductor peak current is about two times the inductor average current, thereby requiring high DC-bias characteristics, which is worse when the output power is high. In this study, a new parallel driving method of two sets of interleaved boost PFC converters for highly pulsating high-power application is proposed. The proposed method does not require any additional load-sharing controller, resulting in high efficiency and smaller inductor size.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.1
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• pp.1-8
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• 2019

In this study, a maximum power point tracking (MPPT) algorithm based on the perturb and observe (P&O) method with variable step size is proposed to improve the dynamic response characteristic of MPPT, using the existing P&O method. The proposed algorithm, which we verified by simulation and experiment, can track the maximum power point (MPP) through duty control and consisted of three operation modes, namely, constant voltage mode, fast mode, and variable step mode. When the insolation is constant, the voltage variation of the operating point at the MPP is reduced through the step size reduction of the duty in the variable step mode. Consequently, the vibration of the operating point is reduced, and the power generation efficiency is increased. When the insolation changes, the duty and the photovoltaic (PV) voltage are kept constant through the constant voltage mode. The operating point then rapidly tracks the new MPP through the fast-mode operation at the end of the insolation change. When the MPP is reached, the operation is changed to the variable step mode to reduce the duty step size and track the MPP. The validity of the proposed algorithm is verified by simulation and experiment of a PV system composed of a PV panel and a boost converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.24-31
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• 2008

Power converters are becoming an essential block in modem mobile multimedia application. This paper presents a high performance DC-DC buck converter for mobile applications. Controller of DC-DC buck converter is designed by current-mode control method. An current-mode DC-DC converter is implemented in a standard $0.18{\mu}m$ CMOS process, and the overall die size was $1.2mm^2$. The peak efficiency was 86 % with a switching frequency of $1\sim1.5MHz$ and a maximum load current of 400mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.86-90
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• 2007

An efficient sensing scheme applicable to DC-DC converters is proposed. The output voltage of the DC-DC converter is fed back and converted to a current signal at the input terminal of the sensor to decide if it is in the tolerable range. The comparison is accomplished by a current push-pull action. With the embedded reference current in the sensor realized from the reference voltage. The advantages of the scheme lie in the fairly accurate and efficient implementation in terms of power consumption and chip size overhead compared with conventional voltage-mode schemes as the major parameter in converting voltage to current is determined by (W/L) aspect ratio of the core transistors. In this paper, a DC-DC converter of 5V output from battery range of 2.2V${\sim}$3.6V adopting the proposed sensing scheme is implemented in a 0.35um CMOS process to prove the validity of the scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.277-284
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• 2017

For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.