• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.302-312
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• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.791-799
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• 2008

In this paper, the electromagnetic modeling and network analysis are proposed for design of GTEM cell operating from DC to 18 GHz. 3D electromagnetic numerical analysis models composed of the coaxial mode-converter for the feeder of GTEM cell, 5 m expanded rectangular coaxial transmission line, and the resistive termination load for current and field transmitted from the feeder are developed. Equivalent network model of feeder, transmission line, and termination load in the GTEM cell is also proposed, so the return loss of GTEM cell is calculated using S-parameters using the electromagnetic numerical analysis. To verify the proposed design method, the GTEM cell is designed, constructed and tested, with its size of $5{\times}2.5{\times}1.7\;m$ and operating frequency of $DC{\sim}18\;GHz$.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.675-687
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• 2010

Structural Health Monitoring (SHM) is the science and technology of monitoring and assessing the condition of aerospace, civil and mechanical infrastructures using a sensing system integrated into the structure. Impedance-based SHM measures impedance of a structure using a PZT (Lead Zirconate Titanate) patch. This paper presents a low-power wireless autonomous and active SHM node called Autonomous SHM Sensor 2 (ASN-2), which is based on the impedance method. In this study, we incorporated three methods to save power. First, entire data processing is performed on-board, which minimizes radio transmission time. Considering that the radio of a wireless sensor node consumes the highest power among all modules, reduction of the transmission time saves substantial power. Second, a rectangular pulse train is used to excite a PZT patch instead of a sinusoidal wave. This eliminates a digital-to-analog converter and reduces the memory space. Third, ASN-2 senses the phase of the response signal instead of the magnitude. Sensing the phase of the signal eliminates an analog-to-digital converter and Fast Fourier Transform operation, which not only saves power, but also enables us to use a low-end low-power processor. Our SHM sensor node ASN-2 is implemented using a TI MSP430 microcontroller evaluation board. A cluster of ASN-2 nodes forms a wireless network. Each node wakes up at a predetermined interval, such as once in four hours, performs an SHM operation, reports the result to the central node wirelessly, and returns to sleep. The power consumption of our ASN-2 is 0.15 mW during the inactive mode and 18 mW during the active mode. Each SHM operation takes about 13 seconds to consume 236 mJ. When our ASN-2 operates once in every four hours, it is estimated to run for about 2.5 years with two AAA-size batteries ignoring the internal battery leakage.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.45-52
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• 2006

In this paper, authors propose a step-up converter of pulse width modulation (PWM) and power factor correction (PFC) by using a novel loss-less snubber. The proposed converter for a discontinuous conduction mode (DCM) eliminates the complicated circuit control requirement and reduces the size of components. The input current waveform in the proposed converter is got to be a sinusoidal form of discontinuous pulse in proportion to magnitude of ac input voltage under the constant duty cycle switching. Thereupon, the input power factor is nearly unity and the control method is simple. In the general DCM converters, the switching devices are fumed-on with the zero current switching (ZCS), and the switching devices must be switched-off at a maximum reactor current. To achieve a soft switching (ZCS and ZVS) of the switching turn-off, the proposed converter is constructed by using a new loss-less snubber which is operated with a partial resonant circuit. The result is that the switching loss is very low and the efficiency of converter is high. Some simulative results on computer and experimental results are included to confirm the validity of the analytical results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.737-740
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• 2001

This paper proposes a new ballast that is ignited by internal LC resonance of buck converter. In order to cancel the steady state current ripple, the proposed ballast utilizes the coupled inductor filter which minimizes the size and weight of the ballast. The operation mode of the proposed ballast is analyzed and the performance of the new ballast is verified by the experimental results from a HOW prototype ballast for metal halide discharge (MHD) lamp.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.522-524
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• 1994

This paper presents power factor and distortion improvement methods via active boost converter and mode select. This method not only reduces the current and voltage distortion but also the physical size and expected low cost. Optimum parameter values arc derived to minimize the harmonise in the input current. A theoretical analysis, simulation and experimental results arc presented.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.152-155
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• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.431-432
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• 2012

The proposed dc-dc convertor for a battery energy storage system(BESS) can reduce the power rating and bidirectional power flow. This system consist soft-switching bidirectional dc-dc converter so it can reduce the energy loss when charging and discharging mode. Thus it can achieve high efficiency. Also, overall system utilizes the voltage compensation circuit. It is composed of small size and low cost due to reducing the power rating. In this paper, we proposed system about verified by simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2369-2379
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• 2013

A CMOS x-ray line scan sensor which is used in both medical imaging and non-destructive diagnosis is designed. It has a pixel array of 512 columns ${\times}$ 4 rows and a built-in DC-DC converter. The pixel circuit is newly proposed to have three binning modes such as no binning, $2{\times}2$ binning, and $4{\times}4$ binning in order to select one of pixel sizes of $100{\mu}m$, $200{\mu}m$, and $400{\mu}m$. It is designed to output a fully differential image signal which is insensitive to power supply and input common mode noises. The layout size of the designed line scan sensor with a $0.18{\mu}m$ x-ray CMOS image sensor process is $51,304{\mu}m{\times}5,945{\mu}m$.